Micron Technology Incorporated

Apple Inc.

Round Rock Research, LLC

Micron Communications, Inc.

Steven F Schicht

Mark E Tuttle

John R Tuttle

Rickie C Lake

Jeffrey P Wright

William R Weier

Donald M Morgan

In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

Clock pulse generation circuit

Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.

Redundancy implementation using bytewise shifting

Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.

Level shifting dynamic write driver

A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described.An RFID tag and interrogator may each include a transmitter and a receiver. The tag and interrogator may communicate with each other at different frequency bands and may communicate in accordance with a wireless communication protocol.

Method and apparatus for RFID communication

A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described.Flexible radio frequency identification (RFID) devices are coupled to a roll of flexible material. Each RFID device coupled to the roll is advanced into a wireless communication region. An antenna in the region separately communicates with each of the RFID devices in a manner that isolates the communication from other REID devices counted to the roll outside the region.

Method and apparatus for communicating with RFID devices coupled to a roll of flexible material

A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger signal is also presented as an input to the passgate. When enabled, the passgate propagates the trigger signal to an output. A predetermined time after the trigger signal appears at the passgate input, a passgate control signal is turned off, thereby preventing the trigger signal from further passing through the passgate. The reset circuit is then turned on, which pulls the signal at the output of the passgate to a reference voltage, ending the pulse. Once the pulse is generated, it can be rectified and further combined with other signals to produce signals used in other parts of the circuit.

Method and apparatus for generating a pulse

A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described.

In-sheet transceiver testing

A method and apparatus are disclosed for selecting either an external column address or an internal column address in a synchronous memory device. The external or internal address is selected by decoding command signals applied to the memory device. If the command signals correspond to a read or a write memory access, an external column address is selected. If the command signals correspond to a burst read or write memory access, an internal column address is selected. Significantly, the command signals are decoded prior to the transition of a clock signal that initiates a memory access so that a column address decoder is already connected to the proper column address source prior to the start of a memory access.

Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device

A test circuit in a memory device includes test data read paths and test data write paths for performing data compression to more quickly test the memory cells in the memory device. The memory device includes first and second banks of memory cells having a redundancy plane defined between the two banks and including at least one data terminal. The test circuit includes a test mode terminal adapted to receive a test mode signal, and a test data write path coupled to a plurality of memory cells in the first and second banks. The test circuit further includes a first test data read path coupled to a plurality of memory cells in the first bank, and a second test data read path coupled to a plurality of memory cells in the second bank. A test data write circuit is coupled to the data terminal and to the test data write path and transfers test data placed on the data terminal over the test data write path to a plurality of memory cells in the first and second banks. A test data read circuit is coupled to the first and second test data read paths. The test data read circuit drives a first error signal active when data on the first test data read path is different from predetermined binary values. The test data read circuit drives a second error signal active when the data on the second test data read path is different from predetermined binary values.

Growing community of inventors

Boise, ID, United States of America

Steven F Schicht