Pmc-sierra, Inc.

Steven F Lang

Charles Kevin Huscroft

Winston K Mok

Carl Dietz McCrosky

Richard Cam

Larrie Simon Carr

Winston Ki-Cheong Mok

David Walden Wong

Vernon Robert Little

Bernard Guay

Richard Tse

Richard Arthur John Steedman

Doug Konkin

Glenn Kenneth Bindley

Gordon A Penner

A bus interface for transfer of SONET/SDH data that supports a plurality of SONET/SDH flows. The invention supports two line coding schemes: 8B/10B encoding of STS-12, and SONET scrambled coding for STS-12, STS-48, and STS-51. The invention additionally supports two modes of line testing: entire links can be tested by inserting and checking PRBS sequences, and the SPE payload of the largest concatenated STS-Nc which the link can carry (STS-12c, STS-48c, STS-51c) can be individually tested by inserting and checking PRBS sequences.

Bus interface for transfer of multiple SONET/SDH rates over a serial backplane

This invention provides a bus interface to connect SONET/SDH termination devices with payload processing devices while utilizing a minimum number of signals. The bus interface of this invention can scale with future advances in bandwidth in serial link technology.

Bus interface for transfer of SONET/SDH data

A method of reducing error-multiplication due to error events in a cell stream transmitted as a plurality of cell sub-streams which includes the steps of receiving an incoming cell stream in the form of an ordered sequence of cells including payload cells, transmitting the incoming cell stream in a round robin fashion on a plurality of physical links such that the ordered sequence of cells is transmitted as a plurality of cell sub-streams, with each cell sub-stream having a multiplexed set of cells from the incoming cell stream, and inserting stuff (st) cells into the cell sub-streams so as to form continuous streams of data. Sequence number cells which are inserted periodically into each cell sub-stream, are used to align the cell sub-streams in frames. Sets of cell location information for the cell sub-streams are encoded and contain the location of payload cells and st cells located within a corresponding cell sub-stream. The sets of cell location information are passed on to a receiving end where they are re-constructed at the receiving end. A sequence of the ordered sequence of cells from the cell sub-streams is re-constructed including decoding the sets of cell location information to identify and locate errored cells and missing cells within the cell sub-streams and demultiplexing and releasing error-free payload cells from the cell sub-streams.

ATM inverse multiplexing system

A multi-channel network device for interfacing between a plurality of physical data links and a control processor, where each physical data link is characterized by a data stream of data packets communicated according to a data link control protocol. The multi-channel network device includes a plurality of receive-side line interfaces, with each with each receive-side line interface having at least one channel associated therewith. Each receive-side line interface is operative to receive incoming data packets from one of the physical data links such that each incoming data packet is received in at least one incoming data segment. Each receive-side line interface is also operative to determine a time-slot number for each incoming data segment arriving thereon.

Multi-channel encoder/decoder

An ATM inverse multiplexing cell-based system for reducing error-multiplication due to error events in the transmitted cell stream, which includes a first IMA assembly having an input coupled to an incoming cell stream from a first ATM layer device, a second IMA assembly having an output coupled to a second ATM layer device, a plurality of links coupling the first IMA assembly to the second IMA assembly. The first IMA assembly includes a multiplexer for multiplexing the incoming cell stream onto the plurality of links and for inserting onto the links framing cells in the form of 'st' cells in place of idle cells and 'S' cells to mark divisions in each channel corresponding to a given number of cells or a given time interval between successive 'S' cells. An encoder encodes and inserts cell location information of both control cells and payload cells. The second IMA assembly includes a plurality of link buffers for receiving cells transmitted along respective ones of links. A demultiplexer demultiplexes cells by aligning 'S' cells on the link buffers and releasing payload cells for CDV smoothing. A decoder extracts and decodes location information from the framing cells to identify errored or missing cells and to mark the location of those cells. A discriminator distinguishes between errors in a header and errors in a payload of an errored cell and flushes all cells in the same frame on each link upon failure to identify an 'unknown' cell before encountering buffer overflow.

A digital data transmission system of a type that uses NRZ line coding, comprising apparatus for generating data sequences comprising at least flag sequences and packet data, a frame generator for assembling scrambled data sequences, into frames for transmission to a receiver, and a self synchronous scrambler for continuously scrambling the data sequence including the flag sequences and packet data, and delivering the resulting scrambled data sequence to the frame generator.

Self-synchronous packet scrambler

A method of interfacing between a non-continuous stream of cells of data and a continuous stream of frames of data, which includes transforming an incoming non-continuous cell stream into a continuous transmitted stream by inserting idle or non-assigned cells into the data stream during idle periods. The cells in the continuous stream are then mapped sequentially and contiguously onto the payload portions of frames. The frames are then transmitted synchronously.

Integrated user network interface device

A method of detecting a pulse density violation in the T1 transmission of digital signals, which includes counting bits in sets of 'k' successively in n serial stages generating an empty-out signal on detection of an 'empty' set of 'k' bits, and generating a pulse density violation on detecting a second set of 'k' zero bits in the 'n' stages of bits at a time when the empty-out signal is present.

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Vancouver, Canada

Steven F Lang