Lsi Corporation

Seagate Technology Incorporated

Steven F Faulhaber

Luke Everett McKay

Joshua P Sinykin

Brian K Einsweiler

Matthew Freel

Mark A Gaertner

Brian Thomas Edgar

Christopher L Hill

Jason McGinley

Vidya Krishnamurthy

Yong Yang

Kevin Nghia Dao

Shuangyi Tang

ChuanPeng Ong

Warren R Volz

Srikanth Methuku

Bryce L DeClercq

David P Bremer

Steven Jerome Spaulding

An event that indicates unexpected shutdown of a hard disk drive is determined. The hard disk includes first and second controllers that control respective first and second independently-operable actuators. Each of the actuators has one or more heads that access one or more spinning disks of the hard disk drive. While receiving power for the hard disk drive via back-electromotive force of a motor driven by the one or more spinning disks in response to the event, the first and second controllers independently move the respective first and second actuators to safe positions. In response to determining the first and second actuators are in safe positions, write cache data associated with the first and second controllers is written to a non-volatile memory.

Managing unexpected shutdown in a disk drive with multiple actuators and controllers

An imminent state reset of a data storage device is detected. In response to determining volatile data of the data storage device could be lost in response to the state reset, the volatile data of the data storage device is stored to a backup memory of the data storage device together with first header data that facilitates recovering the volatile data. The backup memory includes non-volatile, solid-state memory. In response to determining the volatile data would not be lost in response to the state reset, second header data is stored in the backup memory. After the state reset, a recovery of the volatile data from in the backup memory is attempted if the first header data is detected, or a host device is alerted if neither the first header data or second header data is detected.

Protecting volatile data of a storage device in response to a state reset

Mass storage uses additional error correction codes. The additional codes can be stored in a storage medium (e.g., volatile solid state memory) separate from the associated data. The additional codes may be written to a nonvolatile medium. The additional codes may be transient. The additional codes may be cached. As long as present, the additional codes may be used to correct user data in synch with or in addition to other error detection and correction codes.

Transiently maintaining ECC

Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an error sensed on the link. Based on the at least one counter, the SAS/SATA device determines whether to maintain the first signal rate. The link is re-established at a second signal rate based on the determination such that the second signal rate is lower than the first signal rate.

Methods and systems for improving communication throughput of storage links

Methods and structure described herein provide for detecting data inversions between electronic devices in communication with one another and automatically correcting those that inversions. An electronic device may be configured with a receiver that is configured for receiving differential serial data from a transmitter of another electronic device. The differential serial data is formatted according to a particular communication protocol associated with the electronic devices. The receiver detects an invalid sequence in the received differential serial data, such as an inverted SAS primitive, and automatically change the receive logic of the receiver such that subsequent received differential serial data is in the proper polarity. The transmitting device does not require notification of the change in receive logic.

Automatic correction of data polarity on a differential serial bus

Apparatus, systems, and methods for testing SAS cables by applying a signal to one end of a SAS cable, receiving the signal from another end of the SAS cable, and generating an output of information relating to the testing. The testing apparatus may test one or more configuration characteristic of the SAS cable, including, for example a crossover status, a polarity status of transmit ('TX') wires, and a polarity status of receive ('RX') wires.

Apparatuses and methods for determining configuration of SAS and SATA cables

Methods and systems for customizing information in a memory associated with a SAS host bus adapter ('HBA'). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e.g., common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e.g., board trace number, SAS address, configuration page, boot record, etc.). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Methods and systems for integrating unique information in SAS interface components

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Colorado Springs, CO, United States of America

Steven F Faulhaber