Samsung Electronics Co., Ltd.

Steven Eugene Tharp

Jack C Wybenga

Patricia Kay Sturm

Youngil Kim

Joseph Parchersky

A routing apparatus comprising: 1) a first router coupled to a first plurality of Ethernet links; and 2) a second router coupled to a second plurality of Ethernet links, wherein selected ones of the first plurality of Ethernet links are coupled to selected ones of the second plurality of Ethernet links to thereby form Ethernet trunk groups in which traffic associated with a plurality of Ethernet ports are aggregated into a single logical port. The routing apparatus further comprises a first high-speed link and a second high-speed link directly coupling the first router and the second router and forming a self-healing ring for transferring data packets between the first and second routers. In response to a failure associated with the failing one of the first and second routers, the first and second high-speed links transfer data traffic from the failing router to the non-failing router.

Apparatus and method for architecturally redundant ethernet

A router for interconnecting N interfacing peripheral devices. The router comprises routing nodes coupled to one another via switching circuitry. A first routing nodes comprises: 1) a physical medium device (PMD) module for transmitting data packets to and receiving data packets from the N interfacing peripheral devices; 2) an ingress processor for receiving incoming data packets from the PMD module; 3) an egress processor for transmitting data packets to the PMD module; and 4) a medium access control (MAC) processor for forwarding data packets from the ingress processor to the switching circuitry and forwarding data packets from the switching circuitry to the egress processor. The MAC processor determines whether a first data packet received from the ingress processor is directed to the egress processor and, if so, transfers the first data packet directly to the egress processor without forwarding the first data packet through the switching circuitry.

Apparatus and method for hairpinning data packets in an Ethernet MAC chip

A system and method is disclosed for synchronizing a plurality of processors in a processor array. The system and method synchronizes data communications between the processors by regulating memory access of the processors to memory bytes of an asynchronous variable memory. Each memory byte in the asynchronous variable memory is a 'read full and write empty' memory byte. Except for a system processor, each processor in the process array can only write data to an empty memory byte and can only read data from a full memory byte. The processors are prevented from untimely overwriting data and from untimely reading data. This keeps the data communications between the processors properly synchronized.

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Garland, TX, United States of America

Steven Eugene Tharp