Advanced Micro Devices Corporation

Steven E Raasch

Yasuko Eckert

David Andrew Roberts

Greg Sadowski

Andrew Gregory Kegel

Sergey Blagodurov

Seyedmohammad SeyedzadehDelcheh

Onur Kayiran

Maurice B Steinman

Jagadish B Kotra

Manish Satyapal Gupta

Gabriel H Loh

John Kalamatianos

Vilas K Sridharan

Maxim V Kazakov

Shomit N Das

Mitesh Ramesh Meswani

Michael Warren Boyer

Mark Henry Oskin

Shrikanth Ganapathy

Matthew R Poremba

Jieming Yin

Daniel I Lowell

Wayne Burleson

Muhammad Shoaib Bin Altaf

Weon Taek Na

Doug Hunt

A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

Enhanced page information co-processor

An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected lifetime table to indicate an expected lifetime of the data in the non-volatile memory.

Setting durations for which data is stored in a non-volatile memory based on data types

Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.

Method and apparatus for providing wear leveling

Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

Encoding of symbols for a computer interconnect based on frequency of symbol values

Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

Method and apparatus for providing thermal wear leveling

A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

Distributed coherence directory subsystem with exclusive data regions

A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.

Adaptive cache management based on programming model information

A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.

Defense mechanism for non-volatile memory based main memory

A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.

Memory access response merging in a memory hierarchy

Temporal link encoding, including: identifying a data type of a data value to be transmitted; determining that the data type is included in one or more data types for temporal encoding; and transmitting the data value using temporal encoding.

Temporal link encoding

An electronic device includes a non-volatile memory and a controller. The controller receives data to be written to the non-volatile memory and determines a type of the data. Based on the type of the data, the controller selects a given duration of the data from among multiple durations of the data in the non-volatile memory. The controller sets values of one or more parameters for writing the data to the non-volatile memory based on the given duration. The controller writes the data to the non-volatile memory using the values of the one or more write parameters.

An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.

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Boston, MA, United States of America

Steven E Raasch