Oak Technology, Inc.

Steven E Olson

Ning Eric Zhou

Jhy-Ping Shaw

Robert R Griffith

Dan Salmonsen

Ning (Eric) Zhou

A computer system or computer system main memory is provided. The computer system includes a secondary memory and a buffer. The buffer is one having a faster access time than the secondary memory, and data placed within the buffer can be controlled by a control block configured with a control field and a byte count value of data bytes transferred during a DMA cycle, or a chain of DMA cycles. A counter may be used to increment the byte count within one or more control blocks during transfer of data bytes from secondary memory to the buffer. A requester is coupled to forward a read request that is serviced from the buffer if an address of the read request is included within an address incremented by the byte count. Both the control blocks and the buffer can be contained within a main memory local to the requester. Each control block includes a pointer field which points to a respective storage region of the buffer, and also contains the byte count field incremented during transfer of data bytes to one or more of the storage regions. If the previous read request address incremented by the byte count value encompasses the current read request address, then the current read request will be serviced entirely from the faster buffer rather than the slower secondary memory.

Computer system and method for tracking DMA transferred data within a read-ahead local buffer without interrupting the host processor

A computer system, bus interface unit, and method is provided for noting a control block transfer at which an interrupt occurs. The control block is but one control block within a chain of control blocks necessary to effectuate a chain of DMA transfers. If the control block undergoes an interrupt, that control block must be noted and control information associated therewith placed within a register so that when the DMA transfers are resumed, that control block can be immediately pointed to rather than having to initiate the first control block of the chain up to and including the control block undergoing interrupt. By purposely programming interrupts within the tag field of select control blocks and maintaining a software tag register within system memory, a control block within an expanded number of control blocks within a chain can be kept track of and pointed to following an error-induced interrupt. The software-induced interrupts are therefore purposely distinguishable from error-induced interrupts, and are used to extend the range of the hardware tag register normally fixed in size within the DMA controller.

Software enlarged tag register and method thereof for noting the completion of a DMA transfer within a chain of DMA transfers

A computer system includes a host computer and a peripheral memory device such as a CD ROM which are interconnected by a bus including a plurality of pipes defined by packets, time division multiplexing, frequency division multiplexing, or code division multiplexing. A plurality of pipe configuration registers are maintained for controlling bus configuration. A BUS controller for the bus includes a plurality of registers for controlling data transfer including pipe data flow direction, packet size, control information, bandwidth setting, and descriptor pointer. The plurality of pipes can have different bandwidths and latencies to efficiently facilitate the transfer of commands, data, and control information. The peripheral memory device is able to transfer and receive data directly to and from the host computer using a dedicated pipe without the need of a buffer memory at the peripheral device.

System and method for transferring data using separate pipes for command and data

A method and apparatus for dynamic chaining of DMA operations that includes a count to keep track of control blocks associated with such operations when appended to a current chain of control blocks. The count is checked by a DMA controller upon completing the data-transfer operation associated with each block or each control-block chain depending on the use of a wait bit. Memory used to hold control blocks may be preallocated with anticipated control blocks associated in a predefined linked list to avoid the need for subsequently updating existing control blocks when new blocks are appended to a chain.

High speed dynamic chaining of DMA operations without suspending a DMA controller or incurring race conditions

A personal computer capable of creating a table of contents (TOC) for a CD-ROM in response to receipt of lead-in Sub-channel Q data from a CD-ROM disc drive. The personal computer includes a computer readable memory storing a first and second set of instructions. The first set of instructions implement a read lead-in command to read lead-in Sub-channel Q data of the CD-ROM in the CD-ROM disc drive. The second set of instructions create a TOC and store the TOC in the computer readable memory in response to receipt of the lead-in Sub-channel Q data from the CD-ROM disc drive.

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Los Altos, CA, United States of America

Steven E Olson