Nvidia Corporation

The University of North Carolina at Chapel Hill

Nividia Corporation

Steven E Molnar

Mark J French

John Stephen Montrym

Cass Watson Everitt

Emmett Michael Kilgariff

David Kirk McAllister

Adam Clark Weitkemper

Jerome Francis Duluk, Jr

John Erik Lindholm

John H Edmondson

James Leroy Deming

James M Van Dyke

Michael J M Toksvig

John M Danskin

Phillip Craig Keslin

Peter B Holmqvist

Gary C King

Christian Amsinck

David Brian Glasco

Walter E Donovan

Douglas A Voorhies

Bengt-Olaf Schneider

Rui Bastos

Franklin C Crow

George R Lynch

Daniel P Wilde

Timothy John Purcell

Gary M Tarolli

Narayan Kulshrestha

Henry Packard Moreton

Ziyad Sami Hakura

Sean Jeffrey Treichler

Robert Anthony Alfieri

David B Kirk

Roger L Allen

Johnny S Rhoades

Jonathan J Dunaisky

Michael F Harris

Jay Gupta

Ashutosh Pandey

David L Anderson

Matthew Nicholas Papakipos

John Wood Poulton

James Michael O'Connor

Edward Anthony Hutchins

Dale L Kirkland

Patrick Rene Marchand

Rui Manuel Bastos

Patrick Richard Brown

Harold Robert Feldman Zatz

James P Roberts

Robert Ohannessian

Justin S Legakis

Douglas Sim Dietrich

Karan Mehra

Robert J Stoll

James C Bowman

Jay Huang

Matthew J Craighead

Donald A Bittel

Jeffrey M Smith

Amit Pabalkar

William Craig McKnight

Luke Y Chang

John G Eyles

Stuart F Oberman

Lacky V Shah

John Matthew Burgess

Samuel Hammond Duncan

Eric Brian Lum

Stephen Donald Lew

Michael C Shebanow

Abraham Benjamin De Waal

Wishwesh Anil Gandhi

Alexander Lev Minkin

Gregory Muthler

Parthasarathy Sriram

Mark Hairgrove

James D Kelly

Bryon S Nordquist

Colyn Scott Case

Michael Wasserman

James Robertson

Brian D Hutsell

Walter Robert Steiner

Christopher Thomas Cheng

John S Rhoades

John Kelley

Cynthia Ann Edgeworth Allison

Vyas Venkataraman

Lukito Muliadi

Anurag Chaudhary

Franciscus W Sijstermans

Justin Cobb

Blaise A Vignon

Hemayet Hossain

Michael Asbury Woodmansee

Mark Allen Mosley

Jonathon Stuart Ramsay Evans

Weizhong Xu

Bandwidth shaping mechanisms in a memory hierarchy operate a first bandwidth shaper on a first memory, such as a cache memory, to shape bandwidth to a second memory, such as a Dynamic Random Access Memory, and replenish the first bandwidth shaper from a second bandwidth shaper based on a hit bandwidth on the first memory.

Dynamic memory bandwidth shaping

Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

Managing a programmable cache control mapping table in a system level cache

Managing a system level cache

Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

High bandwidth extended memory in a parallel processing system

One embodiment of the present invention includes a memory management unit (MMU) that is configured to efficiently process requests to access memory that includes protected regions. Upon receiving an initial request via a virtual address (VA), the MMU translates the VA to a physical address (PA) based on page table entries (PTEs) and gates the response based on page-specific secure state information. To thwart software-based attempts to illicitly access the protected regions, the secure state information is not stored in page tables. However, to expedite subsequent requests, after the MMU identifies the PTE and the corresponding secure state information, the MMU stores both the PTE and the secure state information as a cache line in a translation lookaside buffer. Advantageously, the disclosed embodiments protect data in the protected regions from security risks associated with software-based protection schemes without incurring the performance degradation associated with hardware-based 'carve-out' memory protection schemes.

Storing secure state information in translation lookaside buffer cache lines

A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Method and system for implementing multi-stage translation of virtual addresses

A system and method for decompressing compressed data (e.g., in a frame buffer) and optionally recompressing the data. The method includes determining a portion of an image to be accessed from a memory and sending a conditional read corresponding to the portion of the image. In response to the conditional read, an indicator operable to indicate that the portion of the image is uncompressed may be received. If the portion of the image is compressed, in response to the conditional read, compressed data corresponding to the portion of the image is received. In response to receiving the compressed data, the compressed data is uncompressed into uncompressed data. The uncompressed data may then be written to the memory corresponding to the portion of the image. The uncompressed data may then be in-place compressed for or during subsequent processing.

System and method for frame buffer decompression and/or compression

Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

System and method of protecting data in dynamically-allocated regions of memory

One embodiment of the present invention sets forth a technique for converting alpha values into pixel coverage masks. Geometric coverage is sampled at a number of 'real' sample positions within each pixel. Color and depth values are computed for each of these real samples. Fragment alpha values are used to determine an alpha coverage mask for the real samples and additional 'virtual' samples, in which the number of bits set in the mask bits is proportional to the alpha value. An alpha-to-coverage mode uses the virtual samples to increase the number of transparency levels for each pixel compared with using only real samples. The alpha-to-coverage mode may be used in conjunction with virtual coverage anti-aliasing to provide higher-quality transparency for rendering anti-aliased images.

Alpha-to-coverage using virtual samples

A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a second portion of the framebuffer data for each one of the multiple samples to compute per-channel differences for each one of the multiple samples and testing the per-channel differences against a threshold value to determine a threshold comparison result. Finally, the method comprises compressing the framebuffer data for the tile based on the reduction ratio, the equality comparison result and the threshold comparison result to produce output framebuffer data for the tile.

Alternate reduction ratios and threshold mechanisms for framebuffer compression

A system and method are described for compressing image data using a combination of compression methods. Compression method combinations are provided to compress image data of a particular frame buffer format and antialiasing mode. Each method in the compression method combination is tried in turn to compress the image data in a tile. The best method that succeeded in compressing the image data is encoded in the compression bit state associated with the tile. Together, the compression bits, the compression method combination, and the frame buffer format provide sufficient information to decompress a tile.

Selecting and representing multiple compression methods

A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

System and method for protecting data by returning a protect signal with the data

Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.

Coalescing to avoid read-modify-write during compressed data operations

One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Order-preserving distributed rasterizer

One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for 'early' Z-testing is possible or whether the Z-test function should be deferred until after shading operations for 'late' Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.

Optimizing a graphics rendering pipeline using early Z-mode

Growing community of inventors

Chapel Hill, NC, United States of America

Steven E Molnar