Xilinx, Inc.

Xlnx, Inc.

Steven E McNeil

Jason J Moore

James D Wesselkamper

Edward S Peterson

Schuyler E Shimanek

Wayne Edward Wennekamp

Roger D Flateau, Jr

Adam Elkins

James A Walstrum, Jr

Lawrence C Hung

Lester S Sanders

Thomas H Strader

Yatharth K Kochar

Shalin Umesh Sheth

Stephen M Trimberger

Boon Yong Ang

Chidamber Kulkarni

Andrew W Lai

John D Corbett

Mikhail A Wolf

Krishna C Patakamuri

Ramakrishna G Poolla

Danny Tsung-Heng Wu

Joe E Leyba

Theodore A Ennis

Scott B Schlachter

Kevin A Mefford

An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

Mixed storage of data fields

Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.

System-on-chip having secure debug mode

A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.

Efuse bank and associated anchor bits

Protecting circuit designs can include, in response to receiving a first encrypted public key, generating, using a hash circuit within the integrated circuit, a first hash of the first encrypted public key. The first hash can be compared with a second hash that was previously stored within a non-volatile memory of the integrated circuit. In response to determining that the first hash matches the second hash, the first encrypted public key is decrypted resulting in a first decrypted public key. A determination is made whether received configuration data for the device is authentic using the first decrypted public key.

Asymmetric protection of circuit designs

Apparatuses, systems, and methods for detecting changes to an IC are disclosed. In an example implementation, an apparatus includes an electromagnetic (EM) sensor. A high-resolution analog-to-digital converter (ADC) is configured to quantize a segment of the EM signal of an IC measured by the EM sensor. The quantized segment of the EM signal is unique to process-voltage-temperature (PVT) characteristics exhibited by the IC. The apparatus also includes a processing circuit configured to prompt the high-resolution ADC, via a control signal, to produce the quantized segment of the EM signal. The processing circuit determines a first signature from the quantized segment and retrieves a baseline signature corresponding to the IC from a data storage circuit. In response to the first signature being different from the baseline signature, the processing circuit indicates that a change to the IC is detected.

Electromagnetic verification of integrated circuits

One approach for authenticating data includes storing a plurality of combinations of representations of public keys and session key IDs in a non-volatile memory. A payload and accompanying public key, session key ID, and signature of the payload are input. The signature is a function of the payload and a private key of a key pair that includes the accompanying public key and the private key. Authenticity of the payload is determined based on the accompanying public key and session key ID and the combinations stored in the non-volatile memory, and from the signature and the payload. In response to determining that the payload is authentic, the payload is processed, and in response to determining that the payload is not authentic, processing of the payload is disabled.

Authentication using public keys and session keys

A system generally relating to an SoC, which may be a field programmable SoC ('FPSoC'), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Secured booting of a field programmable system-on-chip including authentication of a first stage boot loader to mitigate against differential power analysis

A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.

Image file generation and loading

An embodiment of a technique to transfer data between two different interfaces is disclosed. The embodiment of the technique includes: manipulating data arriving at a first data interface with a first word width into data with a second word width; transferring the manipulated data to a second data interface having the second word width; and selecting one of a plurality of different word widths for one of the first or second word widths.

Method and apparatus for transferring data between two different interfaces

A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.

Method and apparatus for memory control with a programmable device

A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Method and apparatus for arbitration among multiple ports

An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to generate SSTL-compliant output. The input buffer circuit includes a first single-ended buffer coupled to a first voltage source and to a ground voltage. The first single-ended buffer has an input coupled to one of the bi-directional pins and has an output coupled to the control logic of the memory controller.

Low power SSTL memory controller

In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a core module for providing one or more output signals. The device comprises an output logic module for receiving the one or more output signals and an input logic module, wherein the one or more output signals are received by the input logic module via one or more feedback paths, where the one or more output signals are forwarded back to the core module.

Method and apparatus for providing a feedback path for an output signal

A programmable logic device (PLD) includes electrically programmable fuses that may be programmed with an identifier of the PLD. The PLD also includes programmable tiles and an interface port that is coupled to a shift register and a subset of the programmable tiles. The interface port includes a control port and a first and second serial data signals. The shift register has a parallel input port to load the identifier from the set of electrically programmable fuses in response to a read command of the control port. The shift register serially shifts by one bit in response to a shift command of the control port, including shifting a bit from the subset of the programmable tiles to the shift register via the first serial data signal and shifting a bit from the shift register to the subset of the programmable tiles via the second serial data signal.

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Rio Rancho, NM, United States of America

Steven E McNeil