Texas Instruments Corporation

Steven E Marum

Charvaka Duvvury

Amitava Chatterjee

Kenneth L Williams

Christopher Michael Graves

Dening Wang

James Craig Spurlin

Janet L Wise

Dale P Stein

Sam M Weaver

Karl-Heinz Kraus

Michael O Chaine

Methods and apparatus to decode dual-tone signals are disclosed. An example receiver to decode a dual-tone signal includes a tone detector to detect a start of a first tone, a first counter to count first cycles of the first tone, a second counter to count second cycles of a system clock while the first counter is counting and the first count is less than a first threshold, state control logic to start the second counter counting third cycles of the clock when a time period elapses, the third count being substantially equal to the second count, the first counter to count fourth cycles of a second tone while the third cycles are counted, and a decoder to compare the fourth count to a second threshold to identify an event represented by the signal.

Methods and apparatus to decode dual-tone signals

In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.

ESD clamp with 'trailing pulse' suppression

An input circuit is designed with an external terminal (104). A first input transistor (108) has a control gate coupled to the external terminal by a low resistance path (104). The first input transistor has a current path coupled to an output terminal (120). A first series transistor (110) has a control gate and a current path. The current path of the first series transistor is connected in series with the current path of the first input transistor. A primary clamp (102) is coupled to the external terminal.

Low resistance input protection circuit

An integrated circuit (10) with ESD protection is provided. The integrated circuit (10) includes a clamping device (28) connected to an input pad (12) of the integrated circuit and to ground (22). The clamping device (28) limits the peak voltage of an ESD pulse applied to the input pad (12) by conducting it to ground (22). A protection device (16) is connected to an input pad (12) of the integrated circuit (10) and to ground. The protection device (16) discharges the energy of the ESD pulse to ground. The protection device (16) is coordinated with the clamping device (28) such that the clamping device (28) turns on before the protection device (16).

Semiconductor ESD protection circuit

A control circuit for a low-voltage bus switch where the control circuit keeps the bus switch open by stealing power from switch I/O terminals during the loss of supply voltage and thereby maintaining bus isolation. The control circuit also provides a good high level and presents a low switch impedance.

Low-voltage bus switch maintaining isolation under power-down conditions

Circuitry (10) and structures (30) are provided for electrostatic discharge protection. A first bipolar transistor (Q1) has a collector electrically coupled to a first node (12), a base electrically coupled to a second node, and an emitter electrically coupled to a third node (14). A second bipolar transistor (Q2) has a collector, a base electrically coupled to the second node, and an emitter electrically coupled to the first node (14). The second bipolar transistor (Q2) supplies a base current to the base of the first bipolar transistor (Q1) in response to the first node (12) reaching a threshold voltage relative to the third node (14), so that the first bipolar transistor (Q1) conducts current between the first (12) and third (14) nodes in response to the base current.

Circuitry and structures for electrostatic discharge protection

An electrostatic discharge protection circuit 11 coupled between an input pad 12 and operational circuitry 20 includes a primary clamp circuit 14 coupled to input pad 12, and a current limit circuit 16 coupled to primary clamp circuit 14. Primary clamp circuit 14 clamps an electrostatic discharge voltage to a first voltage value. Operational circuitry 20, susceptible to damage due to an electrostatic discharge, is coupled to current limit circuit 16 and a zener diode 30 is coupled between current limit circuit 16 and a ground potential. Zener diode 30 has a cathode terminal coupled to current limit circuit 16 and an anode terminal coupled to ground potential. Zener diode 30 further clamps a voltage across operational circuitry 20 to a second voltage which is less than 10 V, thereby protecting operational circuitry 20 from damage due to electrostatic discharge.

ESD protection circuits using Zener diodes

A semiconductor structure (30) is provided for electrostatic discharge protection. A first bipolar transistor (Q1) has a collector electrically coupled to a first node (12), a base electrically coupled to a second node, and an emitter electrically coupled to a third node (14). A second bipolar transistor (Q2) has a collector, a base electrically coupled to the second node, and an emitter electrically coupled to the first node (14). The second bipolar transistor (Q2) supplies a base current to the base of the first bipolar transistor (Q1) in response to the first node (12) reaching a threshold voltage relative to the third node (14), so that the first bipolar transistor (Q1) conducts current between the first (12) and third (14) nodes in response to the base current.

Semiconductor structure for electrostatic discharge protection

The specification discloses circuitry for compensating integrated circuits for negative internal ground voltage glitches. An output transistor (30) receives input signals at its base and has an emitter connected through a Schottky diode (32) to internal circuit ground. The compensation circuit includes a transistor (42) coupled to the base of transistor (30) and having an emitter also coupled to internal circuit ground. A capacitor (44) is connected between the base of transistor (42) and a source of bias voltage. Transistor (42) is rendered conductive by the occurrence of negative voltage glitches on the circuit ground, thus reducing voltage on the base of transistor (30) to prevent premature conduction by transistor (30).

Method and circuitry for compensating for negative internal ground

A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V.sub.cc power supply and ground (32) nodes by using a 'graded turn-on.' Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.

Integrated circuit distributed geometry to reduce switching noise

An electronic system, such as an electronic timepiece, utilizes multi-level, integrated injection logic circuitry and a liquid crystal display. A low-power voltage regulator is provided for driving the liquid crystal display which has a negative temperature coefficient. The voltage regulator provides a negative temperature coefficient which tracks the negative temperature coefficient of the liquid crystal display by utilizing the multi-levels of the integrated injection logic circuit to provide the electrical equivalent of a plurality of series-connected diodes without additional current drain.

Voltage regulator for integrated injection logic electronic system with

An electronic system such as an electronic timepiece includes multi-level, integrated injection circuitry and a multiplexed liquid crystal display. A low-power voltage regulator is provided for driving the liquid crystal display and a current regulator is provided for driving the integrated injection logic circuitry. The current regulator is stacked between the logic levels in order to provide a fractional regulated voltage for driving the liquid crystal display without additional circuit elements and associated current drain.

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Sherman, TX, United States of America

Steven E Marum