Nec America, Inc.

Nec Corporation

Steven E Hossner

Brian F Reilly

Rolf H Wendt

Jeremy H Smith

A local clock system for generating a local clock signal whose frequency and phase are synchronized to the frequency and phase of an external input clock reference signal, wherein the output local clock signal is a non-integer multiple of the input clock reference signal. A numerically controlled generator generates the clock output signal, and the frequency and phase thereof are controlled by a digital tuning word input thereto. An input frequency divider divides the input clock reference signal by a first constant k.sub.11 or a second constant k.sub.22, and an output frequency divider for dividing the output signal by a first constant k.sub.11 or a second constant k.sub.21. A relay-phase detector receives output signals from the input frequency divider and the output frequency divider, and produces a 0 or a 1 output, which controls the input frequency divider to divide by k.sub.12 or k.sub.22 and controls the output frequency divider to divide by k.sub.11 or k.sub.21, causing the input frequency divider and the output frequency divider to shift from one set of constants k.sub.12 and k.sub.11 to the second set of constants k.sub.22 and k.sub.21 upon a change in state of the output signal of the relay-phase detector. A phase accumulator is coupled to the output of the relay-phase detector, for detecting the accumulated phase output of the relay-phase detector, and the output thereof controls the numerically controlled signal generator.

Local clock generator

An enhanced B3ZS decoder which substantially improves error-multiplication performance is disclosed. A string of four bits is examined to detect whether it satisfies two specific criteria. The first criterion is that every valid zero-substitution pattern is immediately preceded by a 'one' bit. The second criterion is that successive zero-substitution BPVs are of opposite polarity. When these criteria are met, the appropriate bits are set to zero, effectively replacing the identified pattern with the original three-zero pattern.

Enhanced B3ZS decoder and method for identifying true zero-substitutions

An AC current limiter, which is connected in series with a transmission line and which operates in two modes, a conductive mode and a protective mode, includes first and second transistors coupled in parallel with first and second diodes, respectively and the emitters of the first and second transistors serially coupled by a sensing element. First and second gain control networks are couple to the first and second transistors, respectively, to permit control of the gain in the first and second transistors. More particularly, as line current increases to a limiting value, the circuit operates in the protective mode. The voltage across the sensing causes a transistor in one of the first and second networks to turn on, thus diverting current from the respective first and second transistors connected in series with the transmission line. Therefore, line current is limited to a predetermined value. When the current through the circuit reverses, the other transistor and respective gain control network limits current flowing in the opposite direction.

In-line AC current limiter

A low frequency high voltage AC power for a telephone system is provided by a ring signal generator, which produces a ring signal from a DC power supply using a pair of switches controlled by pulse width modulation (PWM) circuit. The ring signal generator includes a PWM circuit driving a pair of MOSFET transistors via a respective pair of opto-isolators. The output of the MOSFET transistor switches is commonly connected to a low pass filter network. The ring signal generator of the present invention advantageously produces a 65 VRMS ring signal at very high efficiency.

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Hillsboro, OR, United States of America

Steven E Hossner