Sun Microsystems, Inc.

Vlsi Technology, Inc.

Steven E Golson

John F McDonald

Edward H Frank

Gerald L Frenkil

Scott J Griffith

Edward A Dean

A computer system consisting of a host processor, memory and peripheral devices coupled via a bus which provides emulation of a microprocessor by coupling the microprocessor to the bus. The host processor provides emulation of microprocessor peripherals such that a microprocessor based system is supported and executes processes. A takeover mechanism is provided to enable the host processor to temporarily takeover the microprocessor to perform certain tasks. The host processor causes an interrupt to occur in the microprocessor and monitors the bus cycles initiated by the microprocessor to determine when the microprocessor performs fetches of the routine to service the interrupt. The host processor intercepts fetches for information regarding the location of the interrupt service routine and provides information that causes the microprocessor to execute code of a process to be executed during the takeover. For example, during the takeover, noninvasive debugging of the microprocessor can be performed. Alternatively, a context switch of processes can be performed during the takeover whereby the microprocessor will continue processing in the context of the process stored in the microprocessor. Once the takeover is complete, the host processor places the microprocessor in a state for normal processing after which normal processing by the microprocessor continues.

Method and apparatus for performing a takeover of a microprocessor

A method is provided for writing directly to a frame buffer which provides signals to an output display of a computer system. The computer system has a first processor running a window management program controlling the furnishing of data in a first format to the frame buffer, and a second processor running application programs in a second format for display. A signal is provided from the second processor to the window management program indicating that an application program running on the second processor has information to be displayed. Then a window is set up for the display of the application program running on the second processor under control of the window management program. The second processor is signaled that the window exists and provided information regarding the position and clipping of the window. A data structure is set up for the window including a frame buffer address and clipping information for each address to be generated for displaying the application program running on the second processor in the window constructed. Data is transferred from the application program running on the second processor to the addresses in the frame buffer pointed to by the addresses in the data structure.

Method and apparatus for writing directly to a frame buffer

In the system of the present invention, a specialized form of read-ahead, write-behind buffering is provided which enables the host processing system to provide timely responses to device requests that are emulated by the host processor. Each input/output device request is identified by an address to which the device is purportedly mapped to. This address is translated to an address containing a status word for that particular device being emulated. Each status word contains a byte of information either to be sent to the microprocessor as a response during an I/O read operation request by the microprocessor, or to receive data written by the microprocessor in response to an I/O write operation request, and a plurality of status bits which identify the state of the data contained in the I/O status word. Thus, microprocessor I/O write operations may be quickly performed without the need for immediate response by the host processor and responses for various I/O devices emulated can be precomputed and input to the corresponding I/O status words such that when the microprocessor issues a read request to an input/output device the response may be quickly retrieved and returned back to microprocessor with little or no detected response time degradation.

System for emulating I/O device requests through status word locations

A DRAM allows for hidden refresh of its memory cells. The refresh is performed during a refresh cycle at the beginning of a clock cycle. Immediately before the beginning of each clock cycle the DRAM selects a word line for a row of memory cells for which a data access is to be performed. The DRAM also selects at least one word line for at least one row of memory cells for which a refresh is to be performed. During the refresh cycle, a refresh is performed on every memory cell row which is selected for data access or which is selected for refresh. After the refresh cycle, during a data access segment of the clock cycle, the DRAM continues to select the word line for the row of memory cells for which a data access is to be performed; however, the DRAM no longer selects the at least one word line for at the least one row of memory cells selected for refresh. During the data access segment of the clock cycle, the data access is performed on the row of memory cells which remain selected.

Hidden refresh of a dynamic random access memory

A multi-input logic gate is disclosed having particular application for use as an AND or OR gate in a digital circuit. The OR gate of the present invention includes drive, sense and reference rails. A plurality of input lines are coupled to a gate of a plurality of N-channel transfers disposed between the drive and sense rails, one input line per transistor. The drive rail is coupled to ground through an N-channel transistor whose gate is controlled by the state of a detect line. The sense and reference rails are coupled to a voltage source (V.sub.dd) through P-channel transistors whose gate is also coupled to the detect line. The P-channel transistor coupled to the sense rail is sized to pass more current than the corresponding transfer on the reference rail. A sense amplifier is coupled to the sense and reference rails, and outputs a predetermined signal as a function of the voltage difference of the rails. In operation, a precharge circuit first precharges the drive, sense and reference rails to a known voltage. Signals are then applied to the inputs and allowed to stabilize. A detect signal is generated which turns on the P-channel transistors coupled to the sense and reference rails, and the N-channel transistor coupled between the drive rail and ground. In the event all inputs are low, the sense rail voltage rises faster than that of the reference rail, this voltage difference is sensed by the sense amplifier which outputs a predetermined signal indicating no inputs are high. In the event that one or more inputs are high, the corresponding N-channel transfer coupled between the drive rail and the sense rail is turned on, thereby pulling the sense rail toward ground. The sense amplifier senses that the reference rail voltage exceeds that of the sense rail outputs a signal indicating that at least one input is high. The present invention further includes an improved AND gate which permits an efficient determination of whether all of a multiplicity of inputs are true.

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Carlisle, MA, United States of America

Steven E Golson