Advanced Micro Devices Corporation

Steven E Bourland

Michael P Duane

An improved series-connected transistor architecture and a method for forming the same are provided. Gate conductors for series connected transistors are patterned such that gate conductors on either side of a merged source/drain region which will not be contacted in the completed circuit are spaced more closely together than other gate conductors. In an embodiment of the method, these closely-spaced gate conductors have a spacing between facing sidewalls of less than about twice the expected sidewall spacer width for the process. After a first dopant impurity introduction, a conformal dielectric layer is deposited and portions of the dielectric layer are removed to form sidewall spacers. In the region between the closely-spaced gate conductors, the spacers are merged to form a continuous dielectric. This dielectric protects the substrate between the closely-spaced gate conductors from subsequent impurity introduction and salicide processes. In an alternate embodiment, dielectrics are formed between and adjacent to all gate conductors using dielectric deposition and chemical-mechanical polishing. All dielectrics except those between the closely-spaced gate conductors are subsequently removed, and spacers are formed on exposed sidewalls of the gate conductors.

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W. Lafayette, IN, United States of America

Steven E Bourland