Arm Limited

Steven Douglas Krueger

Seow Chuan Lim

Jamshed Jalal

Christopher Neal Hinds

Jonathan Curtis Beard

Klas Magnus Bruce

Anitha Kona

Carl Wayne Vineyard

Richard Andrew Paterson

Yuval Elad

Ramnath Bommu Subbiah Swamy

Simon Crossley

An apparatus includes processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters in association with a partition identifier and configuration application circuitry applies the set of memory transaction parameters in respect of memory transactions issued by the software execution environment that identifies the partition identifier. The memory transaction parameters comprise a minimum target allocation of a resource used by a memory system in handling the memory transaction that identifies the partition identifier. Also provided is an apparatus that comprises processing circuitry for performing data processing in response to instructions of a software execution environment. Configuration storage circuitry stores a set of memory transaction parameters and associated partition identifiers. The memory transaction parameters comprise resource allocations for handling transactions that identify the associated partition identifier. Configuration application circuitry performs the resource allocations. The memory transaction parameters comprise an enable setting and the configuration application circuitry inhibits the resource allocations based on the enable setting.

Memory transaction parameter settings

An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request. The stash request handling circuitry is then responsive to the corresponding physical address determined by the address translation circuitry to cause the block of data to be stored at a location within the storage structure associated with the physical address.

Apparatus and method for handling stash requests

An apparatus includes processing circuitry configured that performs data processing in response to instructions of one of a plurality of software execution environments. First stage partition identifier remapping circuitry remaps a partition identifier specified for a memory transaction by a first software execution environment to a internal partition identifier to be specified with the memory transaction issued to at least one memory system component. In response to a memory transaction to be handled, the at least one memory system component controls allocation of resources for handling the memory transaction or manage contention for the resources in dependence on a selected set of memory system component parameters selected in dependence on the internal partition identifier specified by the memory transaction. Second stage partition identifier remapping circuitry dynamically overrides the internal partition identifier to be specified with the memory transaction based on a sideband input signal and the first stage partition identifier remapping circuitry indicates, for the partition identifier, whether the second stage partition identifier remapping circuitry is to be used.

Mapping partition identifiers

Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry). The selected partition identifier space and partition identifier together represent information for selecting, at a memory system component, parameters for controlling allocation of resources for handling the memory access request or managing contention for said resources, or for selecting whether performance monitoring data is updated in response to the memory access request.

Partition identifier space selection

An apparatus has processing circuitry to perform data processing, at least one architectural register to store at least one partition identifier selection value which is programmable by software processed by the processing circuitry; a set-associative cache comprising a plurality of sets each comprising a plurality of ways; and partition identifier selecting circuitry to select, based on the at least one partition identifier selection value stored in the at least one architectural register, a selected partition identifier to be specified by a cache access request for accessing the set-associative cache. The set-associative cache comprises: selecting circuitry responsive to the cache access request to select, based on the selected partition identifier, a selected cache maximum associativity value; and allocation control circuitry to limit a number of ways allocated in a same set for information associated with the selected partition identifier to a maximum number of ways determined based on the selected cache maximum associativity value.

Limiting allocation of ways in a cache based on cache maximum associativity value

Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction. Programmable constraint storage circuitry stores at least one resource control parameter constraint used to constrain updating or usage of memory system component resource control parameters.

Constraints on updating or usage of memory system component resource control parameters

Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction, or can control, depending on the partition identifier specified by the memory transaction, whether performance monitoring data is updated in response to the memory transaction. Page table walk memory transactions may be assigned a different partition identifier to the partition identifier assigned to the corresponding data/instruction access memory transaction.

Partition identifiers for page table walk memory transactions

A request for data from a cache (TLB or data/instruction cache) specifies a partition identifier allocated to a software execution environment associated with the request. Allocation of data to the cache is controlled based on a set of configuration information selected based on the partition identifier specified by the request. For a TLB, this allows different allocation policies to be used for requests associated with different software execution environments. In one example, the cache allocation is controlled based on an allocation threshold specified by the selected set of configuration information, which limits the maximum number of cache entries allowed to be allocated with data associated with the corresponding partition identifier.

Partitioning TLB or cache allocation

An apparatus is provided comprising processing circuitry to perform data processing in response to instructions of one of a plurality of software execution environments. At least one memory system component handles memory transactions for accessing data, with each memory transaction specifying a partition identifier allocated to a software execution environment associated with the memory transaction. The at least one memory system component is configured to select one of a plurality of sets of memory transaction progression parameters associated with the partition identifier specified by a memory transaction to be handled. Memory transaction progression control circuitry controls progression of the memory transaction in dependence on the selected set of memory transaction progression parameters.

Memory partitioning

An apparatus comprises partition identifier storage storing an instruction partition identifier and a data partition identifier. When issuing a memory transaction for accessing data, the transaction is issued specifying a partition identifier depending on the data partition identifier, while when the memory transaction is for accessing an instruction, the transaction specifies a partition identifier depending on the instruction partition identifier. A memory system component selects one of a number of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. The memory system component controls allocation of resources for handling the memory transaction or manages contention for the resources in dependence on the selected set of parameters, or updates performance monitoring data specified by the selected set of parameters in response to handling of said memory transaction.

Partitioning of memory system resources or performance monitoring

A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

Correlating local time counts of first and second integrated circuits

Memory transactions are issued to a memory system component specifying a partition identifier allocated to a software execution environment associated with said memory transaction. The memory system component selects one of a plurality of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. The memory system component controls allocation of resources for handling the memory transaction or manages contention for the resources in dependence on the selected set of parameters, or updates performance monitoring data specified by the selected set of parameters in response to handling of said memory transaction. Partition identifier remapping circuitry is provided to remap a virtual partition identifier specified for a memory transaction by a first software execution environment to a physical partition identifier to be specified with the memory transaction issued to the memory system component.

An apparatus comprises two or more partition identifier registers, each corresponding to a respective operating state of processing circuitry and specifying a partition identifier for that operating state. The processing circuitry issues a memory transaction specifying a partition identifier depending on the partition identifier stored in a partition identifier register selected based on the current operating state. The memory system component selects one of a number of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. The memory system component controls allocation of resources for handling the memory transaction or manages contention for the resources in dependence on the selected set of parameters, or updates performance monitoring data specified by the selected set of parameters in response to handling of said memory transaction.

A data processing system includes a memory controller which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

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Austin, TX, United States of America

Steven Douglas Krueger