Advanced Micro Devices Corporation

Steven Dines

Adrian Sfarti

Mohammad Y Maniar

Andrew D Daniel

A circuit and method for a display controller especially adapted for display memories organized in arrays. The invention permits high speed modification of the contents of a display by generating the address signals of a selected linear pattern as the data block to be modified is retrieved from the display memory. For vectors, the addresses are generated in the same time as required for data block retrieval. The invention also permits calculation of the addresses of simple curves as the data block to be modified is retrieved, though calculation times typically are longer than for vectors. Modified Breshenham's algorithm is used for the address calculation.

Rapid graphics bit mapping circuit and method

An apparatus and a method for character and graphics pattern generation in a bit mapped graphics display system is disclosed that includes a pixel data manager 14 for supplying character bit maps and graphics patterns to a visible display memory 22. A character information memory 24 is utilized for the storage of character descriptive information which includes an address table 26, macro-instructions 28, 30, and 32, and character bit maps 34, 36, and 38. Each character in a set of characters has an associated macro-instruction and character bit map. The address table contains memory addresses that point to the macro-instructions. Each macro-instruction contains executable instructions that establish the size and location of a corresponding character bit map. To supply a character to the visible display memory, the pixel data manager fetches and executes a corresponding macro-instruction. Overhead burden on the central processing unit is minimized.

Apparatus and method for displaying characters in a bit mapped graphics

A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode logic block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer to transmit data signals from the peripheral device to a system bus. The circuit also provides for a second slave mode logic block and a master mode logic block for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer to transmit data signals from the system bus to the peripheral device. Each slave mode logic block is responsive to condiion signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the periphel device so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.

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San Jose, CA, United States of America

Steven Dines