Imec Vzw

Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Steven Demuynck

Chao Zhao

Boon Teik Chan

Zheng Tao

Soon Aik Chew

Julien Ryckaert

Praveen Raghavan

Stefan Cosemans

Liesbeth Witters

Silvia Armini

Efrain Altamirano Sanchez

Zsolt Tokei

Eugenio Dentoni Litta

Eddy Kunnen

Gerald Beyer

Marc Schaekers

Roger Palmans

Antony Premkumar Peter

Jürgen Bömmels

Dunja Radisic

Yu Chen-Hua

Chung-Shi Liu

The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor

A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

Split replacement metal gate integration

The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

Method of fabricating stacked semiconductor device

Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.

Method for forming source/drain contacts

A method is provided for blocking a portion of a longitudinal through-hole during manufacture of a semiconductor structure, comprising the steps of: forming a stack comprising a hard mask comprising at least one trench, and a first coating filling the at least one trench and coating the hard mask, wherein the first coating comprises one or more materials that can be etched selectively with respect to a second coating; etching at least one vertical via in the first coating directly above the portion of the trench in such a way as to remove the first coating over at least a fraction of the depth of the trench, filling the at least one via with the second coating material, and removing the first coating selectively with respect to the second coating from at least the one or more longitudinal through-holes in such a way as to leave in place any of the first coating present directly underneath the second coating.

Method for blocking a trench portion

A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

Method for forming a field effect transistor device having an electrical contact

A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

Buried interconnect for semiconductor circuits

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Aarschot, Belgium

Steven Demuynck