Ramtron International Corporation

Steven D Traynor

Donald J Verhaeghe

George Argos, Jr

John D Spano

Shan Sun

Dennis R Wilson

William F Kraus

Lark E Lehman

Ferroelectric switching properties are severely degraded in a hydrogen ambient atmosphere. By controlling the polarity of the capacitors in a ferroelectric memory during the manufacturing process, the amount of degradation can be significantly reduced. After metalization of a ferroelectric memory wafer, all of the ferroelectric capacitors are poled in the same direction. The polarization vector is in a direction that helps to counteract hydrogen damage. A hydrogen gas anneal is subsequently performed to control underlying CMOS structures while maintaining ferroelectric electrical properties. The wafer is then passivated and tested.

Polarization method for minimizing the effects of hydrogen damage on ferroelectric thin film capacitors

A test method for characterizing retention performance, both same state and opposite state performance, of ferroelectric capacitors includes the steps of writing an original complementary data state into first and second ferroelectric capacitors after the ferroelectric capacitors have been initialized into an initial valid data state. The first and second ferroelectric capacitors are then subjected to time and temperature stress. The original complementary data state from the first and second ferroelectric capacitors is then read, and same state charge (Q.sub.SS) information is collected. An opposite complementary data state is then written in the first and second capacitors. After a short time interval, possibly at an elevated temperature, the opposite complementary data state from the first and second ferroelectric capacitors is read to gather opposite state charge (Q.sub.OS) information. The original complementary data state is then written into the first and second ferroelectric capacitors. The first and second ferroelectric capacitors are then subjected to further stress cycles, after which the same state and opposite state charge values are recorded. A plot of the same state charge (Q.sub.SS) and opposite state charge (Q.sub.OS) versus log time can be generated, which has great value for fully characterizing a ferroelectric capacitor and for predicting the performance of a ferroelectric capacitor in a memory circuit.

Method of measuring retention performance and imprint degradation of

A reference cell for a 1T/1C ferroelectric memory includes a transistor of a first polarity type having a gate coupled to a reference cell word line, and a current path coupled between a bit line and an internal reference cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line, and a current path coupled between a source of supply voltage and the internal reference cell node, and a ferroelectric capacitor coupled between the internal reference cell node and ground.

Reference cell for a 1T/1C ferroelectric memory

A circuit and method for reducing compensation of a ferroelectric capacitor in a cell of a memory array allows the capacitor's hysteresis loop to be repositioned toward its uncompensated position by pulsing the electrodes of the memory cell capacitors, via the memory array plate line, one or more additional times whenever a 'write' occurs to the memory array. As a result, the ferroelectric capacitor delivers a signal of greater strength to the memory device sense amps upon a subsequent 'read' operation significantly enhancing overall reliability and yield yet without reducing overall device endurance.

Circuit and method for reducing compensation of a ferroelectric

Circuit and method for reducing a compensation of a ferroelectric

A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer. Similarly, an optional sealing layer such as silicon dioxide, silicon nitride, or polymer based materials can be deposited on top of the passivation layer to prevent any possible contamination of the integrated circuit package by the passivation layer. Once the hard passivation layer and any optional layers are formed, these layers are etched to provide access to underlying integrated circuit bonding pads.

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Colorado Springs, CO, United States of America

Steven D Traynor