Intel Corporation

Steven D Pudar

Niranjan L Cooray

Mark E Bauer

Alaa R Alameldeen

Jayesh Gaur

Sherif R Sweha

Robert L Baltar

Kevin W Frary

Chinnakrishnan S Ballapuram

Manuel A Aguilar Arreola

Margareth E Marrugo

A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.

Cache memory data compression and decompression

A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

Nonvolatile memory blocking architecture

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Folsom, CA, United States of America

Steven D Pudar