Motorola Corporation

Steven D Millman

Sean C Tyler

Thomas J Balph

Alberto J Reyes

Markus G Wloka

James P Garvey

A plurality of serially coupled circuit cells ( ) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is effected by loading on subsequent circuit cells, i.e. downstream loading is conveyed back to the first cell. The capacitance ( ) and resistance ( , of each cell has a loading effect on each previous cell. The effective resistance and capacitive values of each cell is identified and maintained as one element of the distributed serial load model. The distributed serial load accurately models the loading of unbuffered cells ( ). The distributed serial load is also applicable to portions of circuit cells ( ) that are not be buffered and where the downstream loading has an effect on previous circuit drivers ( ).

Method of modeling circuit cells with distributed serial loads

An electronic key validation process increases security by encrypting the security access codes. A key (10) receives data having a hidden polynomial select code and polynomial seed from a host (12). A locally stored (24, 26) select offset and seed offset in the key identifies the location (22) of the select code and seed in the data. The select code decodes (32) into polynomial coefficients which are used to configure a polynomial generator (34). The seed is loaded into the polynomial generator as a starting point of the polynomial. The polynomial generator is clocked a number of cycles to calculate a remainder. The select code is modified (28) to select a new polynomial, and the polynomial generator is clocked another number of cycles. The host runs a similar encryption algorithm. The remainder is sent to the host where it is compared with the host generated remainder for key validation.

Circuit and method of encrypting key validation

A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.

Low power flip-flop circuit and method thereof

A method for determining test pattern fault equivalence. The method comprises selecting a bridging fault (16) from a digital circuit, then determining a stuck-at fault (17) which guarantees detection of the bridging fault. Generation of a test vector (18) which detects the stuck-at fault. Simulating the test vector (19) to find all bridging faults that are detected by the test vector, and repeating the above steps until the desired percentage of detectable bridging faults are examined.

Test pattern fault equivalence

A novel RS latch for use in asynchronous designs has been provided. The RS latch is made scannable by the use of additional circuitry which provides a basis for a scan chain signal to propagate in and out the scannable RS latch. Such a scannable RS latch greatly facilitates the testing of the asynchronous design.

Technique and method for asynchronous scan design

A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).

Test pattern generation

A CMOS logic circuit uses a boost transistor responsive to a pulse signal to rapidly charge and/or discharge the output node during predetermined transitions of the input signal and provide a selectable slew rate for one edge of the output signal. A pulse generator circuit provides the pulse signal of predetermined width at a first transition of the input signal and disables the pulse signal and boost transistor before the following transition to avoid adversely effecting the opposite edge of the output signal. The width of the pulse signal and the size of the boost transistor determines the slew rate of the output signal for the edge under control. Many types of logic circuits such as inverters, NAND gates and NOR gates may utilize dual boost transistors and pulse generator circuits for separate control over both output edge rates without adversely affecting the opposite edge.

Pulsed CMOS logic circuit having selectable rise and fall times

A CMOS transmission gate circuit having a pass transistor and a feedback transistor is coupled across a logic gate. The pass transistor is responsive to a control signal for passing a logic signal. The feedback transistor aids the pass transistor in passing a first logic voltage level when the output signal of the logic gate is a second logic voltage level. Further, the speed performance of the CMOS transmission gate circuit is not degraded if the feedback transistor fails.

Transmission gate having a pass transistor with feedback

When testing one circuit block of a device, it is desired to have isolation from the other circuit blocks of the device so as to prevent possible failure of the other circuit blocks. A block isolation buffer includes a circuit for providing predetermined voltage levels at the inputs of the circuit blocks which are not being tested thereby assuring that an undesired input does not appear at the inputs of the non-tested circuit blocks.

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Mesa, AZ, United States of America

Steven D Millman