Texas Instruments Corporation

Steven D Krueger

Karl M Guttag

Jonathan H Shiell

Roger D Norwood

Duy-Loan T Le

Wilbur Christian Vogley

Anthony M Balistreri

Kenneth A Poteet

Joseph H Neal

Joseph P Hartigan

Ian Chen

Timothy David Anderson

Joseph R Zbiciak

Donald Edward Steiss

David J Hoyle

Jagadeesh Sankaran

David A Comisky

Ashwini K Nanda

Stephen T Walker

Michael J Amundsen

Tai-Yuen Chan

Martha A Branstad

In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

On-demand predicate registers

A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation index vector. An index vector generation circuit is also disclosed.

Method and apparatus for producing an index vector for use in performing a vector permute operation

A method and apparatus is provided for operating a digital system having several processors ( ) and peripheral devices ( ) connected to a shared memory subsystem ( ). Two or more of the processors execute separate operating systems. In order to control access to shared resources, a set of address space regions within an address space of the memory subsystem is defined within system protection map (SPM) ( ). Resource access rights are assigned to at least a portion of the set of regions to indicate which initiator resource is allowed to access each region. Using the address provided with the access request, the region being accessed by a memory access request is identified by the SPM. During each access request, the SPM identifies the source of the request using a resource identification value (R-ID) provided with each access request and then a determination is made of whether the resource accessing the identified region has access rights for the identified region. Access to the identified region is allowed to an initiator resource only if the resource has access rights to the identified region, otherwise an error process is initiated ( ).

System protection map

A digital system is provided with a microprocessor ( ), a cache ( ) and various memory and devices ( ). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) ( ). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit ( ) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.

Cache memory controlled by system address properties

A data processing system ( ) is provided with a digital signal processor (DSP) ( ) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D , .D ) connected to dual memory ports (T , T ) in a level one data cache memory controller ( ). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

Microprocessor with non-aligned memory access

A computer system ( ) comprising a central processing unit ( ) and a memory hierarchy. The memory hierarchy comprises a first cache memory ( ) and a second cache memory ( ). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information ( ) and pixel data ( ). Lastly, the computer system comprises cache control circuitry ( ) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure

A microprocessor (,) comprising a cache circuit (,) and circuitry (,) for issuing a prefetch request. The prefetch request (,) comprises an address (,) and requests information of a first size (,) from the cache circuit. The microprocessor also includes prefetch control circuitry (,), which comprises circuitry for receiving the prefetch request and evaluation circuitry for evaluating system parameters corresponding to the prefetch request. Additionally, the prefetch control circuitry comprises circuitry, responsive to the evaluation circuitry, for determining a size of information for a prefetch operation starting at the address from the cache circuit, where the prefetch operation corresponds to the prefetch request.

Prefetch circuity for prefetching variable size data

A microprocessor (,) for coupling to an external read/write memory (,) having an addressable storage space. This storage space stores cacheable digital data and non-cacheable (,) digital data. The microprocessor includes a data storage circuit (,) for storing a portion of the non-cacheable data. The microprocessor further includes an address storage circuit (,) for storing an address corresponding to the portion of the non-cacheable data. Still further, the microprocessor includes a counter (,) for advancing a count from an initial value (,) toward a threshold value (,) in response to an activity over time. The counter initiates its advancing operation in response to the data storage circuit receiving the portion of the non-cacheable data. Lastly, the microprocessor includes an indicator (,) for indicating the portion of the non-cacheable data in the data storage circuit is expired in response to the count reaching a threshold.

Microprocessor circuits and systems with life spanned storage circuit for storing non-cacheable data

A microprocessor (,) for coupling to an external read/write memory (,) having an addressable storage space for storing data. The microprocessor includes a data storage circuit (,) for storing a portion of the data, where that portion of data comprises non-cacheable data. The microprocessor further includes a class storage circuit (,) for storing a class identifier corresponding to the portion of the non-cacheable data, as well as an input (TERMINATE) for receiving a terminate signal and an input (CLASS) for receiving a class signal. Lastly, the microprocessor includes an indicator (,) for indicating that the portion of the non-cacheable data in the data storage circuit is expired in response to assertions of the terminate signal and the class signal matching the class identifier.

Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

High-speed memory arranged for operating synchronously with a

A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128) is configurable by way of configuration signals (BCFG) to be operable in various bus configurations for communicating signals between a module bus (IBUS) and external buses (XPCI1, XPCI0). These modes include combining the external buses (XPCI1, XPCI0) into a single bus of the 64-bit PCI type, operating the external buses (XPCI1, XPCI0) as separate 32-bit PCI buses, as separate CardBus buses, as separate AGP buses (either at one or multiple data transfers per cycle), or as combinations thereof. Certain of the configuration signals (BCFG) are used to select the clock frequencies at which the external buses (XPCI1, XPCI0) operate, in either of the 64-bit or 32-bit PCI protocols, or in the AGP bus protocol when present. The external buses (XPCI1, XPCI0) may be operable at different speeds, and at different protocols, depending upon the state of the configuration signals (BCFG).

Configurable expansion bus controller in a microprocessor-based system

A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).

Microprocessor system with burstable, non-cacheable memory access support

A digital computing system (30). The digital computing system includes a memory (36) and a memory controller (34). The memory comprises at least one memory bank (B0), and that bank comprises a plurality of rows (R.sub.0 -R.sub.N) and a plurality of columns (C.sub.0 -C.sub.N). The memory controller circuit is coupled to control the memory, and comprises a first bus (38) for providing an address to the memory, and three additional buses (38, 40). A first of these additional buses provides a row address strobe signal (RAS*) to the memory, where assertion of the row address strobe signal represents an indication that an address on the bus is a valid row address directed to one of the plurality of rows. A second of these additional buses provides a column address strobe signal (CAS*) to the memory, where assertion of the column address strobe signal represents an indication that an address on the bus is a valid column address directed to at least one of the plurality of columns. A third of these additional buses provides a bank close signal (BC*) to the memory, where assertion of the bank close signal represents a request to the memory to immediately de-activate an active one of the plurality of rows.

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Dallas, TX, United States of America

Steven D Krueger