Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Steven Craig Bartling

Sudhanshu Khanna

Charles M Branch

Scott Robert Summerfelt

Michael Zwerg

Hugh Pryor McAdams

John Anthony Rodriguez

Dharin Nayeshbhai Shah

Wei-Yan Shih

Michael Patrick Clinton

Mark Jung

Andreas Waechter

Krishnasawamy Nagaraj

Brian Roger Elies

Hao Meng

Christy Leigh She

Markus Kösler

Marc Edward Royer

Marko Krüger

Huang-Chun Wen

Yogesh Kumar Ramadass

Ralf Peter Brederlow

Per Torstein Roine

James Robert Hochschild

Aatmesh Shrivastava

Gregory Allen North

Juergen Luebbe

Bharath Siravara

Sankar Prasad Debnath

Soman Purushothaman

Keshav Bhaktavatson Chintamani

Cory Dean Stewart

Joerg Schreiner

Brent Peterson

Leah Trautmann

Pedro R Galabert

Neeraj Mogotra

Samil D Kamath

Andreas Dannenberg

Aik K Goh

Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Customizable backup and restore from nonvolatile logic array

In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

Piezo-electric sensor reset

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Compute through power loss hardware approach for processing device having nonvolatile logic memory

Configuration states for a computing device and/or associated peripherals ('profiles') are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Nonvolatile logic memory for computing module reconfiguration

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Non-volatile counter system, counter circuit and power management circuit with isolated dynamic boosted supply

The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.

Electronic device and method for data processing using virtual register mode

An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.

Differential sensor using thin-film piezoelectric capacitors

Configuration states for a computing device and/or associated peripherals ('profiles') are stored in one or more non-volatile logic ('NVL') arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

Processing device with nonvolatile logic array backup

A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to storea machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

Configuration bit sequencing control of nonvolatile domain and array wakeup and backup

A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.

Piezoelectric sensing apparatus and method

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Plano, TX, United States of America

Steven Craig Bartling