Intel Corporation

Abbott Cardiovascular Systems, Inc.

Steven Chang

Anshuman Thakur

Ramacharan Sundararaman

Ramon Matas

Robert F Netting

Hugo Antonio Cobar

Cynthia R Lee

Lei Zhou

Jay S Lawlor

Julie Pham Mou

Ernest Munoz

David Alves

Expandable electrophysiology catheters having electrodes mounted on splines of an expandable member are described. The splines of the expandable member include subsegments between a proximal location and a distal intersection at a central axis. The subsegments can include respective top-down profiles, and at least one of the top-down subsegment profiles is straight between the central axis and an adjacent top-down subsegment profile. The subsegments can be interconnected to extend continuously about the central axis from the proximal location to the distal intersection. Other embodiments are also described.

Expandable member for an electrophysiology catheter

Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

Boot strap processor assignment for a multi-core processing unit

An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.

Reset of multi-core processing system

Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.

Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit

This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

Initialization of multi-core processing system

This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.

Growing community of inventors

San Jose, CA, United States of America

Steven Chang