Altera Corporation

Steven Caranci

Przemek Guzy

Mark Ari Teper

Alexander Grbic

Deshanand Pratap Singh

Stephen D Brown

Mark Bourgeault

Terry Borer

Ketan Padalia

Tim Michael Vanderhoek

Ivan Hamer

Shawn Malhotra

Jimmy Kuo

Rebecca Katzin

Zvonko Vranesic

A system evaluates a hierarchical name set such as names produced by hardware descriptor language (HDL) synthesis and generates shorter, unambiguous names for each of the hierarchical names in the name set. A directed graph and/or a tree is generated using a hierarchical name set. Each name is evaluated using the directed graph and/or tree to identify hierarchical components or tokens of the name required in the short name. Name length can be reduced even in a system having large numbers of common hierarchies.

Generation of readable hierarchical path identifiers

A method for generating a design for a system to be implemented on a target device includes compiling the design. Information used to make a compilation decision on the design is stored. A strategy to improve timing closure on a signal path on the design is derived using the information.

Method and apparatus for performing automated timing closure analysis for systems implemented on target devices

A graphical block-based design exploration tool displays multiple views of a chip design. These views may include a logical view, physical view, hierarchy view, and a timing display view, displayed side-by-side or sequentially with or without animation. Various entities and their relationships to each other are displayed in these different view arrangements to allow a user to quickly grasp the entire design and to perform design techniques such as partitioning and floor planning. The display properties are user configurable to organize the information based on user preferences.

Graphical block-based design exploration tool

Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of the paths is generated and rendered. In another method, the paths are specified as being associated with modules within the circuit design. In this method, a histogram plot of the paths within each module is generated, wherein the paths within each module are identified as being dominated by routing delay or logic delay. In another embodiment, a connectivity diagram is generated to convey an amount of connectivity within modules and between modules. Each of the methods can be implemented as program instructions on a computer readable medium.

Performance visualization of delay in circuit design

A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A first location on the target device for a first logic region having a first component is determined. Determined properties of the first logic region are preserved. The first logic region is integrated with a second logic region having a second component in view of the determined properties.

Method and apparatus for designing systems using logic regions

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Toronto, Canada

Steven Caranci