Cypress Semiconductor Corporation

Tandem Computers Incorporated

Steven C Meyers

Nathan Y Moyal

John Michael Brown

William F Bruckert

Robert W Horst

S Babar Raza

David J Garcia

Bertrand Jeffery Williams

William P Bunton

John D Coddington

William J Watson

John C Krause

David P Sonnier

Douglas E Jewett

Eric K Bolton

William Edward Baker

Richard W Cutts, Jr

Susan S Meredith

Geoffrey I Iswandhi

Stephen G Low

Daniel L Fowler

Frank A Williams

Patricia L Whiteside

Randall G Banton

Linda Ellen Zalzala

Terry D Little

Paul N Hintikka

Dan Zupcau

Mark J Marlett

James Stevens Klecka

Brian G Kirkland

Gary F Campbell

Curtis Willard Jones, Jr

Michael P Baker

James Stephens Klecka

Barry Lee Drexler

Harry Frank Elrod

A bandgap circuit comprising a current generation circuit and a current replication circuit is provided herein. The output current of the current generation circuit is generated as a weighted sum of two currents. The circuit configuration of the current generation circuit allows it to function at low power supply voltages, e.g., on the order of 1 V. The current replication circuit includes an operational amplifier, which when configured in conjunction with MOS cascode current sources and the current generation circuit, significantly increases the accuracy and insensitivity to power supply noise of the bandgap circuit output current. A resistor may be included between the bandgap circuit output node and ground for generating a reference voltage with increased accuracy and insensitivity to power supply noise.

High PSRR, high accuracy, low power supply bandgap circuit

A charge pump circuit with resistively attenuated inputs is described herein. By reducing a voltage swing of input signals supplied thereto, the charge pump circuit described herein is configured for producing output signals with relatively low static phase offset even when operating at relatively low power supply voltages (e.g., less than about 1.2 volts). In general, the input voltage swing may be reduced by coupling an attenuator to each input of the charge pump circuit. A method for operating the differential charge pump is described, along with exemplary devices (e.g., PLL and DLL devices) within which the charge pump may be utilized.

Low-voltage, low static phase offset differential charge pump

A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

Phase-locked loop and delay-locked loop including differential delay cells having differential control inputs

An apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.

Method/architecture for a low gain PLL with wide frequency range

The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.

Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch

A circuit and method are provided for ensuring a non-desired output state of a latch or flip-flop cannot be produced. The latch can be configured as a set dominant, reset dominant, or memory dominant circuit by simply placing programmed voltage values on select transistors of the latch. The programmed values will cause either the set input, the reset input, or both set and reset inputs to have a complimentary effect on the output signals even though the set and reset inputs are at the same logic level. The set, reset, and memory dominant circuit is identical in structure; however, the set, reset, and memory dominant features are derived solely by placing programmed values on corresponding transistors within the identical structure. A generic latch circuit can, therefore, be said to operate in one of three dominant ways depending on the programmed values chosen by a selector and fed to a prioritizer.

Programmable latch that avoids a non-desired output state

An apparatus comprising a phase lock loop (PLL) and a charge pump. The PLL may be configured to generate an output signal in response to an input signal. The charge pump may be configured within the PLL and be configured to (i) pump-up the input signal, (ii) pump-down the input signal or (iii) enter tri-state in response to a control signal.

Method for charge pump tri-state and power down/up sequence without disturbing the output filter

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a reference voltage. The first current may vary as a function of temperature. The second circuit may be configured to generate a second current to counteract for the variations of the first current. The second current may vary as a function of temperature. The third circuit may be configured to generate a third current in response to the first current and the second current.

Low supply voltage BICMOS self-biased bandgap reference using a current summing architecture

A circuit and method for preventing an oscillator from oscillating above a first predetermined frequency or below a second predetermined frequency. The present invention may comprise (a) a clock generation circuit configured to generate an output clock signal in response to (i) a reference clock, (ii) one or more control signals and (ii) a reset signal and (b) a control circuit configured to generate said reset signal in response to said one or more control signals.

Circuits, architectures and methods for detecting and correcting excess

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Clock circuits for synchronized processor systems having clock generator

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Round Rock, TX, United States of America

Steven C Meyers