Cyrix Corporation

Cisco Technology, Inc.

National Semiconductor Corporation

Other

Motorola Corporation

Via-cyrix, Inc.

Steven C McMahan

Mark W Bluhm

Raul A Garibay, Jr

Mark W Hervin

Michael G Gallup

James G Gay

William B Ledbetter, Jr

John K Eitrheim

Christopher E White

Marc A Quattromani

Ralph C McGarity

Kenneth C Scheuer

Russell Stanphill

Lawrence H Hudepohl

Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

Testing self-repairing memory of a device

A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions has a data dependency on other of the simultaneously issued instructions, detecting circuitry for detecting dependencies between instructions in the pipelines and circuitry for controlling the flow of instructions through the pipelines such that an instruction is not delayed due to a data dependency on another instruction unless the data dependency must be resolved for proper processing of the instruction in its current stage.

Processor with multiple execution pipelines using pipe stage state

A prefetch unit is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. Normally, the prefetch unit performs split prefetching by generating low and high prefetch addresses in a single clock, with the high prefetch address being generated from the low prefetch address by incrementation. In cases where the low prefetch address is supplied to the prefetch unit too late in a clock period to generate the high prefetch address, such as where a branch instruction is not detected by a branch processing unit so that the target instruction address (i.e., the low prefetch address) is supplied by an address calculation stage, the prefetch unit generates a prefetch request consisting of only the low prefetch address. In an exemplary embodiment each prefetch request is for an 8 byte block of instruction bytes, such that the high prefetch address is generated by adding an 8-bit value to the low prefetch address, and, for low prefetch addresses supplied late, the prefetch unit detects whether the low prefetch address has a �0! in bit position 3, and if so, generates the high prefetch address by toggling the bit position n to a �1! (because the no carry ripple will affect the higher order bits).

Adjusting prefetch size based on source of prefetch address

An up/dn read prioritization protocol is used to select between multiple hits in a set associative cache. Each set has associated with it an up/dn priority bit that controls read prioritization for multiple hits in the set--the up/dn bit designates either (i) up prioritization in which the up direction is used to select the entry with the lowest way number, or (ii) dn prioritization in which the down direction is used to select the entry with the highest way number. For each new entry allocated into the cache, the state of the up/dn priority bit is updated such that, for the next cache access resulting in multiple hits, the read prioritization protocol selects the new entry for output by the cache.

Branch processing unit with target cache read prioritization protocol

A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.

Method of identifying and self-modifying code

Address calculation logic in which an adder carry out flags a segment limit violation is used, in an exemplary embodiment, in a 486 type microprocessor. An effective address adder (24) and a three input adder (26) comprise limit checking logic. The three input adder receives on offset (EA�31:0!) and two limit-checking components: the memory reference fetch size and, for the exemplary embodiment, a converted segment limit. Specifically, the segment limit from a segment descriptor is converted such that, for either expand up or expand down segments, when the offset is added to this converted segment limit and (in the case of expand up segments) the fetch size in the three input adder, a limit violation is flagged by the carry out bit of a three input adder. In the exemplary embodiment, the segment is converted at segment load and stored on-chip in a segment descriptor register.

Address calculation logic including limit checking using carry out to

A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.

Condensed microaddress generation in a complex instruction set computer

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache--the far target cache stores limits and mode bits for far targets stored in the target cache. For each far COF entry in the target cache, an FTC index field stores an index pointing to the corresponding entry in the far target cache. For far COFs that hit in the target cache, the target cache outputs corresponding far target addressing information and the associated FTC index to indirectly access the far target cache to obtain the associated segment limit information.

Branch processing unit with a far target cache accessed by indirection

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU implements a branch prediction scheme using a target cache and a separate history cache. The target cache stores target addressing information and history information for predicted taken branches. The history cache stores history information only for predicted not-taken branches. The exemplary embodiment uses a two-bit prediction algorithm such that the target cache and the history cache need only story a single history bit (to differentiate between strong and weak states of respectively predicted taken and not-taken branches).

Branch processing unit with target cache storing history for predicted

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a prefetch block of 16 bytes) are separated into low and high block addresses (addressing split blocks of 8 bytes). The low and high block addresses differ in bit position �3! designated a bank select bit, where the low block address of an associated prefetch request may be designated by a �1 or 0! such that a split block associated with a low block address may be allocated into either bank of the target cache (i.e., the low block of a prefetch request can start on an 8 byte alignment rather than the 16 byte alignment). For each prefetch request that includes both low and high block addresses, respective banks of the target cache are successively accessed based on the state of the bank select bit, such that the low block address is used to access one bank and the high block address is used to access the other bank.

Branch processing unit with target cache using low/high banking to

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return stack for call/returns, including return stack pointer repair in the case of the failure of a call/return to confirm (decode) or resolve. Return stack control logic maintains a return stack pointer, incrementing and decrementing the return stack pointer respectively for call/return pairs that hit in the target cache--in addition, the return stack control logic maintains two additional stack pointers used for repair: (a) a confirmation pointer that is incremented when a call is decoded and decremented when a return is decoded; and (b) a resolution pointer that is incremented when a call resolves, and decremented when a return resolves. If a call/return pair that hits in the target cache is not confirmed, the return stack control logic selectively repairs the return stack pointer by replacing it with the confirmation pointer, while if a call/return pair that hits in the target cache does not resolve, the return stack control logic selectively repairs the return stack pointer by replacing it with the resolution pointer.

Branch processing unit with a return stack including repair using

A prefetch unit includes flow control for controlling the transfer of instruction bytes from a prefetch buffer to a decoder where the prefetch buffer includes predicted change of flow instructions. Instruction bytes in the prefetch buffer are arranged in prefetch blocks--associated with each prefetch block is a flow control bit. When the transfer of instruction bytes from a current prefetch block is complete, the flow control bit is checked--if the flow control bit is set to indicate that the prefetch clock includes a predicted COF instruction, instruction bytes will not be transferred from the next prefetch block unless the predicted COF instruction is confirmed as having been decoded. This flow control avoids the complexity of maintaining information to repair the prefetcher and decoder if the predicted COF instruction is not decoded.

Prefetch buffer using flow control bit to identify changes of flow

A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.

Processor with single clock decode architecture employing single microROM

A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During this period, other logic functions may be performed, including calculation of the propagation bits and generate bits for each adder block.

Growing community of inventors

Richardson, TX, United States of America

Steven C McMahan