Sun Microsystems, Inc.

Oracle America, Inc.

Steven C Krow-Lucal

Drew George Doblar

Thomas Alan Ziaja

Paul J Dickinson

David Jeffrey

William L Robertson

Karl P Dahlgren

James C Hunt

Murali Gala

Poh-Joo Tan

David L Curwen

Dong Tran

Oliver Caty

An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

At-speed scan testing of memory arrays

A high-performance memory module. The memory module is designed for a computer system with a wide data path. The memory module is implemented using a small printed circuit board (PCB), with a plurality of memory chips and a connector mounted upon the PCB. Signal traces for control, address, and data signals are arranged in such a manner as to minimize the length of each signal trace, thereby saving PCB area. On the connector, an electrical ground pin is located between each pair of signal pins, which may allow for a low-resistance return current path, and may therefore allow the module to operate at higher clock frequencies. Furthermore, locating a ground pin between each pair of signal pins may help reduce signal interference, or &ldquo;crosstalk&rdquo;, thereby improving signal integrity of the memory module.

High-performance memory module

A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.

Memory module test system with reduced driver output impedance

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Sunnyvale, CA, United States of America

Steven C Krow-Lucal