Lenovo (singapore) Pte. Ltd.

International Business Machines Corporation

Steven C Jacobson

Luke David Remis

Gregory David Sellman

Michael DeCesaris

Timothy R Tennant

Loc X Nguyen

Brian Christopher Totten

Jeremy Scott Bridges

Milton Cobo

Optimizing an IC bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the IC bus frequency if the calculated rise time is greater than the maximum threshold.

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Allocating lanes in a Peripheral Connect Interface Express ('PCIe') bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

Allocating lanes in a peripheral component interconnect express ('PCIe') bus

Chip select ('CS') multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Chip select ('CS') multiplication in a serial peripheral interface ('SPI') system

According to one exemplary embodiment, a method for reducing electrical component stress from power cycling is provided. The method may include receiving an indication associated with power cycling an electronic apparatus. The method may also include identifying, based on the received indication, a first one or more groups of electrical components that will not be powered off during the power cycling of the electronic apparatus. The method may further include identifying, based on the received indication, a second one or more groups of electrical components that will be powered off during the power cycling of the electronic apparatus. The method may finally include powering off the second one or more groups of electrical components.

Voltage regulator stress reducing system

A system comprises a plurality of fans, wherein each of the fans is configurable to run at a unique fan speed that is different from fan speeds of other fans from the plurality of fans. A plurality of variable-positioned devices, capable of being positioned at various locations within the system, are physically positioned such that airflow from one of the plurality of fans strikes a particular variable-positioned device. A plurality of anemometers, each of which is connected to a particular variable-positioned device, measure airflow across the variable-positioned devices. A system controller, which contains location information that identifies a physical position within the system of each of the plurality of fans, utilizes airflow readings from each of the anemometers to identify a physical location of each of the plurality of variable-positioned devices by matching physical locations of the fans to measured airflow across the variable-positioned devices.

Identifying physical locations of devices within an electronic system

A method auto-switches interfaces between a client computer and subsystems in a device under management. A first output bus from a first subsystem is coupled to a client computer via a multiplexer, wherein the first subsystem is a subsystem from multiple system subsystems in the device under management. A hardware subsystem bus monitor monitors all output busses from the multiple system subsystems for a predetermined event on a bus. In response to the predetermined event being detected on a second output bus from a second subsystem in the device under management, the multiplexor decouples the first output bus from the client computer and couples the second output bus to the client computer.

Auto-switching interfaces to device subsystems

Operating a demultiplexer on an IC bus, the demultiplexer including a set of input signal lines from an IC master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the IC master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.

Operating a demultiplexer on an inter-integrated circuit ('I2C') bus

A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.

Integrated circuit retention mechanism with retractable cover

Detecting data transmission errors in an IC system that includes a source device, an destination device, and a signal line coupling the IC source and destination device, including: receiving, by the IC destination device from the IC source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the IC destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the IC source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the IC source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.

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Mebane, NC, United States of America

Steven C Jacobson