Texas Instruments Corporation

Steven C Goss

Narendar M Shankar

Gregory Remy Philippe Conti

Aymeric S Vial

Mehdi-Laurent Akkar

A secure demand paging system () includes a processor () operable for executing instructions, an internal memory () for a first page in a first virtual machine context, an external memory () for a second page in a second virtual machine context, and a security circuit () coupled to the processor () and to the internal memory () for maintaining the first page secure in the internal memory (). The processor () is operable to execute sets of instructions representing: a central controller (), an abort handler () coupled to supply to the central controller () at least one signal representing a page fault by an instruction in the processor (), a scavenger () responsive to the central controller () and operable to identify the first page as a page to free, a virtual machine context switcher () responsive to the central controller () to change from the first virtual machine context to the second virtual machine context; and a swapper manager () operable to swap in the second page from the external memory () with decryption and integrity check, to the internal memory () in place of the first page.

Methods, apparatus, and systems for secure demand paging and paging operations for processor devices

A secure demand paging system including a secure internal memory, an external non-volatile memory having encrypted and integrity-protected code pages, an external volatile memory for swap pages and a processor coupled to said secure internal memory and to said external non-volatile memory and operable to decrypt and verify the integrity of the code pages thereby to transfer code pages to said secure internal memory directly from said external non-volatile memory bypassing said external volatile memory in respect of the code pages, and to swap out and swap in the swap pages between secure internal memory and said external volatile memory bypassing said external non-volatile memory in respect of the swap pages for said external volatile memory.

Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.

A secure demand paging system includes a processor operable for executing instructions, an internal memory for a first page in a first virtual machine context, an external memory for a second page in a second virtual machine context, and a security circuit coupled to the processor and to the internal memory for maintaining the first page secure in the internal memory. The processor is operable to execute sets of instructions representing: a central controller, an abort handler coupled to supply to the central controller at least one signal representing a page fault by an instruction in the processor, a scavenger responsive to the central controller and operable to identify the first page as a page to free, a virtual machine context switcher responsive to the central controller to change from the first virtual machine context to the second virtual machine context; and a swapper manager operable to swap in the second page from the external memory with decryption and integrity check, to the internal memory in place of the first page.

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Addison, TX, United States of America

Steven C Goss