Texas Instruments Corporation

Steven C Eplett

Scott E Smith

Kallol Mazumder

Matthew R Harrington

Timothy D Dorney

Jason M Brown

Daniel B Penny

John E Riley

Rishad S Omer

A clock buffer circuit ( ) for generating buffered clock signals (CLKI and CLKI_) in response to an external clock signal (CLKX) is disclosed. A first buffer section ( ) drives to a first output node ( ) between high and low logic levels in reponse the CLKX signal. To reverse the adverse effects of noise on the falling edges of CLKX signal, a boost section ( ) and clock generator ( ) are provided. In response to low-to-high transitions at the first output node ( ) the pulse generator ( ) generates a pulse at a pulse output ( ). In response to the pulse, the boost section ( ) provides additional driving capability for further pulling the first output node ( ) to the high logic level. The first output node provides the CLKI_ signal. A second buffer circuit ( ) provides the CLKI signal in response to the CLKI_ signal. An enabling section ( ) is provided for enabling, or alternatively, disabling the preferred embodiment ( ). In addition, a hysteresis section ( ) is also included to introduce hysteresis into the response of the preferred embodiment ( ).

Clock input buffer with increased noise immunity

A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

Circuit and method for internal refresh counter

A method and apparatus for testing a semiconductor serial access memory (30) device through a main memory (20) includes a semiconductor memory comprising a main memory (20) and a serial access memory (30). A test data (48) is generated and an expected test data (50) that is equivalent to the test data (48) is also generated. The test data (48) is stored in the main memory and sent to the serial access memory (30). The test data (48) in the serial access memory is then sent back to the main memory (20) and stored in the main memory (20). The test data (48) is then read from the main memory (20). Then, the test data (48) read from the main memory is compared with the expected test data (50), producing an output having a first state if the test data (48) read from the main memory (20) is similar to the expected test data (50) or a second state if the test data (48) read from the main memory (20) is different than the expected test data (50).

Method and device for testing a semiconductor serial access memory

A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.

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Houston, TX, United States of America

Steven C Eplett