Tektronix, Inc.

Steven C DenBeste

Russell Y Anderson

Daniel C Olin

John D Blattner

Douglas G Boyce

Kenneth K Hillen

An electrical circuit is described that requires a reduced number of data bits for character-address and video-mode information by using a predetermined bit combination of the video-mode information as part of the character-address information. Character-address and video-mode information is output from a random access memory (RAM) to a character read only memory (ROM) and a video-mode detection circuit that produces outputs to enable video-mode circuits in the video control circuitry. One output of the video-mode detection circuit is coupled to an address input of the character ROM that has characters divided into two character sets. A predetermined bit combination of the video-mode information produces an output from the video-mode detection circuit that selects one of the character sets while the other bit combinations produce an output from the detection circuit that selects the other character set. In this way, character-address and video-mode information having n data bits can produce character and video-mode outputs that normally require n+1 data bits.

Character and video mode control circuit

A digital signal sampling system is disclosed for reconstructing the time relationship of digital data signals sampled by two sampling clock signals with different unrelated timebases. The digital data signals sampled may be the same data signal or two different data signals sampled simultaneously in two separate sampler circuits at two different unrelated sampling clock frequencies or timebases to produce first and second sampled data signals. A timebase correlation circuit produces first and second time correlation signals in the form of binary level signals in response to the receipt by a last clock pulse detector of first and second store clock signals which are derived from first and second sampling clock signals. The time correlation signals indicate by their binary level the source of the last previous clock pulse of the first and second store clock signals which was received by the timebase correlation circuit. The timebase correlation signals and the first and second sampled data signals are stored in two acquisition memories connected to such sampler circuits, and are read out of the memories and together with a last clock pulse output of the correlation circuit are applied to a data signal reconstruction means including a digital computer which is programmed to reconstruct the digital data signals in time relationship and to display the reconstructed data signals on a cathode ray tube or other display device.

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Beaverton, OR, United States of America

Steven C DenBeste