Cisco Technology, Inc.

Finisar Corporation

Ii-vi Delaware, Inc.

Hewlett-packard Company

Steven C Bird

Henry Meyer Daghighian

Linda M Mazaheri

Bob Needham

Phuong Rosalynn Duong

Mudasir Ahmad

YongShan Zhang

Stephen K Will

Charles H Casale

Mark S Allen

Gerald Douglas Babel

Varoujan Malian

Danlu Tang

Phillip E Deaver

A circuit includes a printed circuit board including a first portion defining a window formed as a first void on a first side of the printed circuit board and a second portion defining a cavity formed as a second void opposite the first void on a second side of the printed circuit board. The circuit further includes a heat sink inserted in the second void, the heat sink having a first side forming a bottom of the first void and the bottom of the first void within the printed circuit board. The circuit yet further includes at least one electronic circuit die mounted to the first side of the heat sink and electrically coupled to the first side of the printed circuit board.

High-speed hybrid circuit

An optical waveguide is disclosed. In a disclosed embodiment, the optical waveguide includes a first aluminum nitride (AlN) thin film disposed on a layer of high-frequency polymer. A second AlN thin film is embedded in the first AlN thin film. In disclosed embodiments, the nitrogen concentration level of the first AlN thin film is different than the concentration level of the second AlN thin film.

Optical waveguide having aluminum nitride thin film

A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.

Aluminum nitride substrate with graphite foil

Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.

Method of forming micro via in printed circuit board

A hybrid printed circuit board may include a top layer, a bottom layer, and a plurality of internal layers stacked up between the top layer and the bottom layer. The plurality of internal layers may include a first internal layer below the top layer and a second internal layer above the bottom layer. The hybrid printed circuit board may include first unreinforced laminate placed between the top layer and the first internal layer. The hybrid circuit board may additionally include second unreinforced laminate placed between the second internal layer and the bottom layer. The hybrid printed circuit board may include third laminate placed between adjacent internal layers of the plurality of internal layers.

Hybrid PCB with multi-unreinforced laminate

Aluminum nitride substrate

Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards

Optimizing ASIC pinouts for HDI

Connection an integrated circuit on a surface layer of a printed circuit board

Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (&#x3bc;Via) having a conductive dome disposed above the outer layer pad of the &#x3bc;Via. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Conductive dome probes for measuring system level multi-GHZ signals

A drop out trigger captures waveform data when a normally continuous input signal is disrupted or interrupted. In the preferred embodiment, a conventional trigger detects a parameter periodically satisfied by the continuous signal and resets a timer whenever a trigger event occurs. The alarm count of the timer is set for an interval slightly larger than the periodic interval. If the timer reaches the alarm count, a measurement signal is generated.

Growing community of inventors

San Jose, CA, United States of America

Steven C Bird