Intel Corporation

Steven Burns

Eriko Nurvitadhi

Srikanth T Srinivasan

Jonathan D Pearce

Jeffrey J Cook

Asit K Mishra

David B Sheffield

Abhijit Davare

Andrey Ayupov

Anton Alexandrovich Sorokin

Desmond A Kirkpatrick

Patrick R Morrow

Deborah T Marr

Donald W Nelson

Debbie Marr

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Apparatus and method for adaptable and efficient lane-wise tensor processing

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule a plurality of matrix operations responsive to a tensor matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, each lane comprising: first, second, and third tile registers to store blocks of a first matrix (A), second matrix (B), and third matrix (C), respectively; at least one tensor arithmetic logic unit (TALU) to multiply a block of elements of the first matrix with a block of elements of the second matrix to generate a product and to accumulate the product with a block of elements of the third matrix, wherein each lane is to multiply one or more different blocks of the first and second matrix and to accumulate the resulting one or more products with one or more different blocks of the third matrix; and broadcast circuitry to broadcast one or more invariant matrix blocks to different tile registers within a lane and/or different tile registers across different lanes.

An integrated circuit layout is described that uses a library cells with alternating conducting lines. One embodiment includes a first cell and a second cell, the second cell being adjacent to the first cell. The first cell has a first plurality of conductive lines, a first portion of the first plurality having line ends that are a first distance from the second cell. The second cell has a second plurality of conductive lines, the conductive lines being parallel to and aligned with the conductive lines in the first cell, a second portion of the second plurality having line ends that are a second distance from the first cell. The first distance is shorter than the second distance.

Integrated circuit layout using library cells with alternating conductive lines

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Portland, OR, United States of America

Steven Burns