International Business Machines Corporation

Steven Bradford Herndon

Daniel Frank Moertl

Michael Joseph Genden

Eric M Foster

Chuck Hong Ngai

James Wilson Bishop

Michael Joseph Carnevale

Philip Lee Vitale

Eric Eugene Retter

David Allen Hrusecky

Dennis P Cheney

Ronald S Svec

Mark Louis Ciacelli

John David Myers

According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.

Region-weighted accounting of multi-threaded processor core according to dispatch state

An approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational logic determines whether one of the multiple threads is dispatching an instruction and, if so, computes a dispatch weighting value using the selected weighting value and a dispatch factor that indicates a weighting adjustment of the selected weighting value. In turn, a resource utilization value of the selected thread is computed using the dispatch weighting value.

A closed-loop system for dynamically distributing memory bandwidth between real-time components and non-real-time components is provided. Specifically, the present invention includes monitors for measuring a performance of each of the real-time components. Based on the measured performance, closed-loop feedback loop is communicated to a unified memory system. The feedback is used by the memory controls within the unified memory system to efficiently and dynamically distribute memory bandwidth between the real-time and the non-real-time components.

Closed-loop system for dynamically distributing memory bandwidth

A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.

Apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory

Method for implementing enhanced vertical ECC storage in a dynamic random access memory

A method and structure for dynamically blocking access of a request signal R to a shared bus such that R originates from a non real-time master and requests access to an address range of an address space. The shared bus manages requests for access to the address space. The non real-time master and a real-time master compete for access to the address space by presenting address access requests to the shared bus. The dynamic blocking of access by R to the shared bus is accomplished by use of a request limiter, which is a device that is coupled to a real-time clock and uses an algorithm to determine when to enable and disable access of R to the shared bus. The algorithm uses a windowing scheme that permits access of R to the shared bus every N clock cycle, wherein the value of the integer N may be supplied to the request limiter by the real-time master. An example of the algorithm includes blocking access of R to the shared bus whenever all of the following conditions occur: the real-time master has a non-empty internal queue, the real master and the non real master are both requesting access to a same address range of the address space, and the real-time clock is not at the N clock cycle that permits access of R to the shared bus.

Pre-arbitration request limiter for an integrated multi-master bus system

A memory interface for an integrated system is presented which allows simultaneous, transparent access to multiple external memories coupled thereto. The memory interface resides within a functional unit of the integrated system and includes multiple memory ports, at least one of which is coupled to dedicated memory and one port to shared memory. The dedicated memory comprises private memory for the functional unit, while the shared memory is common memory coupled to the functional unit and other functional units of the integrated system. The memory interface has a controller for forwarding memory fetch requests generated by requesting units within the functional unit to the proper memory port as determined at system initialization. A lookahead request generator is employed for generating speculative lookahead fetch requests within the memory interface using information on received memory fetch requests and known memory access patterns. The lookahead fetch requests retrieve data from external memory in anticipation of actual memory fetch requests being generated.

Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests

Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.

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Endicott, NY, United States of America

Steven Bradford Herndon