Tego, Inc.

Other

Transwitch Corporation

Steven Benoit

David Puleston

Leonid Mats

Robert W Hamlin

Timothy P Butler

Javier Berrios

Subhash Chandra Roy

Michael M Renault

Daniel C Upp

Igor Zhovnirovsky

David Toebes

William Lipp

In embodiments of the present disclosure improved capabilities are described for a method and system for a radio frequency (RF) tag comprising a controller, a memory, and a memory manager, wherein the controller utilizes the memory manager to manage different memory types.

RF tag with memory management

In embodiments of the present disclosure improved capabilities are described for a method and system for a radio frequency (RF) tag configured to communicate with a network through a gateway facility, the RF tag comprising (i) an RF and analog block for receiving and transmitting an RF signal, (ii) a data processing and controller block for digital information processing, (iii) a memory store, and (iv) a communication facility, wherein the RF tag is at least in part powered by an external RF signal received by the RF and analog block, and wherein the communication facility transfers data from the RF tag to the gateway facility or transfers data from the gateway facility to the RF tag.

RF tag network connectivity through gateway facility

In embodiments of the present invention improved capabilities are described for a system for collecting aviation flight cycle data comprising a radio frequency (RF) tag configured to read sensor information from a sensor, the RF tag comprising (i) an RF and analog block for receiving and transmitting an RF signal, (ii) a data processing and controller block for digital information processing, and (iii) a memory store, wherein the RF tag is at least in part powered by an external RF signal received by the RF and analog block; and a sensor for generating sensor information indicative of an airborne flight cycle parameter, wherein the RF tag periodically collects the sensor information generated by the sensor and stores the sensor information in the memory store.

Flight-cycle sensor monitoring of aviation component

In embodiments of the present invention improved capabilities are described for a stand-alone RFID sensor apparatus comprising a passive radio frequency identification (RFID) tag configured to read sensor information from a sensor, the passive RFID tag comprising an RF network node and a communication facility, the RF network node comprising (i) an RF and analog block for receiving and transmitting an RFID interrogation signal, (ii) a data processing and controller block for digital information processing, (iii) a memory store, and (iv) a power management block for managing power requirements of the RFID sensor apparatus, and the communications facility linking the sensor and the passive RFID tag, wherein the data processing and controller block manages communication of the sensor information through the communications facility.

RFID tag facility with access to a sensor

In embodiments of the present invention improved capabilities are described for a passive radio frequency identification (RFID) tag, where the passive RFID tag contains an RF network node and communication facility. The RF network node includes an RF and analog block for receiving and transmitting an RFID reader signal, a data processing and controller block for digital information processing, a memory store, and a power management block for managing power requirements of the RF network node. The communication facility communicates at least in part with an external display facility. The distribution of power to the RF network node functional blocks is controlled using the power management block to select between an extended operational time and an increase in available functionality.

RFID tag facility with access to external devices

Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.

Phase and frequency drift and jitter compensation in a distributed telecommunications switch

A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12&times;12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

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Walpole, MA, United States of America

Steven Benoit