Advanced Micro Devices Corporation

Steven Beigelmacher

Michael T Clark

Edward J McLellan

David N Suggs

Kelvin Domnic Goveas

David Edward Kroesche

Luke Yen

Donald A Priore

Mike Butler

In a normal, non-loop mode a uOp buffer receives and stores for dispatch the uOps generated by a decode stage based on a received instruction sequence. In response to detecting a loop in the instruction sequence, the uOp buffer is placed into a loop mode whereby, after the uOps associated with the loop have been stored at the uOp buffer, storage of further uOps at the buffer is suspended. To execute the loop, the uOp buffer repeatedly dispatches the uOps associated with the loop's instructions until the end condition of the loop is met and the uOp buffer exits the loop mode.

Execution of instruction loops using an instruction buffer

A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits.

Processor and method implemented by a processor to implement mask load and store instructions

A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location or an end location for a packet; and making a record of the packet boundaries by setting a hint bit in a hint bit vector, a location of the hint bit within the hint bit vector corresponding to a position of the packet in the stream. The hint bit vector is split into two or more vectors, where the hint bits are assigned to one of the vectors on an alternating basis. The packets of interest are processed corresponding to the hint bits assigned to each vector in parallel over multiple clock cycles, wherein an original order of the packets of interest is maintained in the stream.

Odd and even start bit vectors

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Somerville, MA, United States of America

Steven Beigelmacher