Advanced Micro Devices Corporation

Sharp Kabushiki Kaisha Corporation

Other

Sharp Microelectronics Technology, Inc.

Sharp Electronics Corporation

Steven B Sidman

Eugen Gershon

Philip M Freidin

Rudolph J Sterner

Brendan J Babb

Roy J Levy

Steven Harris

Chwen-Jye Ju

A DSP system is provided for performing FFT computations with low latency by parallel processing of complex data points through a plurality of butterfly FFT execution units. The system simplifies the circuitry required by employing a single address generator for all of the memory units coupled to like ports on each execution unit. All RAM's connected to, for example, the A ports of a plurality of DSP's will be addressed by a single address generator. Similarly, all RAM's connected to the B ports of a plurality of DSP's will be addressed by a single address generator. Simple one-port RAM memory is suitable for use with the invention.

FFT-based parallel system for array processing with low latency

A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional register banks. The register banks then sequentially shared between arithmetic processors connected to the CPU datapath. Each register bank, after being loaded with data, is connected to a plurality of data processors in sequence and the data in each register bank is processed. The data is not moved between register banks within the datapath, except when it is loaded and unloaded from the datapath. The invention takes advantage of the shorter time required to move control signals, as compared with moving data.

Data processing system using a shared register bank and a plurality of

A system and method is provided for use in register-based CPUs for processing data in the CPU register bank while concurrently loading and unloading data into additional register banks. The additional register banks are then sequentially connected to the CPU datapath for data processing. Interconnections between the various register banks in the CPU and appropriate data buses for performing the load/process/unload functions are controlled by a load/store control logic block which can be a simple state machine processor. The load/store control logic is triggered by a software instruction encountered at the end of particular computational routines during normal program execution. This software instruction replaces the need for separate load and store instructions and their attendant clock cycles. The invention substantially decreases unused data processor time since the arithmetic and logic unit (ALU) can be sequentially connected to register banks which have been pre-loaded with data for processing. The need to stop data processing through the ALU while data is loaded into an unloaded from the CPU register bank is eliminated. A method of register-based CPU concurrent I/O operation is also disclosed.

Multiple register bank system for concurrent I/O operation in a CPU

The present invention addresses the need in the art by providing a novel approach to the correction of errors in check bits in an encoded data word. The invention consists of a check bit output latch 16 which stores check bits generated by a check bit generator 14 and outputs the newly generated check bits to memory 12 when a single error occurs in the word located in the check bits. The data is corrected so the newly generated check bits are correct and can be latched out to memory 12 at the same time the data is latched out. The invention includes a syndrome generator 18, an error corrector 34, and an error detector 36. The present invention provides a powerful performance boost to error detection and correction circuits by correcting check bits in memory with newly generated check bits when no errors in the data word are detected.

Error detection and correction circuit

A full duplex optical signal transmission system comprising a pair of transceivers interconnected by means of a single fiber optic cable is provided with an optical receiver for detecting transmitted and received optical signals and a delay and compensation circuit used in conjunction with a differential amplifier coupled to the optical signal receiver for separating the transmitted optical signal from the received optical signal for providing an output from the transceiver comprising a signal corresponding to the received optical signal.

Transceiver for full duplex signalling on a fiber optic cable

In a circuit for selectively communicating data into and out of a signal path, typically used for diagnosing a data processing unit, a shadow register is used for receiving data from and transferring data to an external source. The shadow register is physically insulated from the signal path by a first state register and a second state register, the first state register transferring data from the signal path to the shadow register, the second state register transferring data between the shadow register and the signal path. Path switching is achieved by a selector connected to the respective outputs of the first and second state registers and responsive to a control signal for releasing output signals from only one of these registers.

Diagnostic circiut for digital systems

An output current control circuit (10) for use with CMOS output buffers so as to reduce significantly ground bounce noise, includes a variable resistance device (28) for limiting the maximum short circuit current in a pull-down transistor (N1) so as to reduce significantly ground bounce noise. A feedback resistor (R.sub.s) is used to sense a reference voltage developed at a system ground reference line (30) for controlling the resistance of the variable resistance device (28).

Output current control circuit for reducing ground bounce noise

There is disclosed herein a servo data decoder which can decode both quadrature and non quadrature servo data. The decoder is comprised of a servo data amplitude demodulator to generate position error signals and a position error signal processor to generate a GPES signal to serve as a position error signal during the track following mode and a velocity signal and a track crossing signal for use in the seek mode. The user system may have either single or double pulse sync, and double pulse sync spacing, pulse window time and sync to first data pulse delay are user definable. The user may adjust the gain of the system in two manners and may program the frequency response characteristics of the phase locked loop. Many other user definable or user alterable features are provided.

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Vancouver, WA, United States of America

Steven B Sidman