Texas Instruments Corporation

Steven Arthur Vitale

Freidoon Mehrad

Shaofeng Yu

Joe G Tran

James Walter Blatchford

Benjamen M Rathsack

Hyesook Hong

Craig Henry Huffman

A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device

A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.

Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device

In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to pattern first features. The method can also include forming a second mask layer over the first features, using the second mask layer to pattern portions of the first features, removing the second mask layer, and removing the first mask layer.

Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach

A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a conductive material, such as polysilicon, is formed over the gate dielectric layer. The gate layer is patterned to form a gate electrode having a first horizontal dimension. One or more growth-stripping operations are performed to reduce a critical dimension of the gate electrode to a second horizontal dimension, where the second horizontal dimension is less than the first horizontal dimension.

Gate CD trimming beyond photolithography

Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device

A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

Method of forming silicided gates using buried metal layers

A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and partially etching the layer to form lateral and vertical surfaces. Thicknesses of one to several atomic diameters of atoms that comprise said layer are removed from the lateral surfaces and the vertical surfaces that are located under the mask to form a target dimension of a semiconductive device structure.

Manufacturing a semiconductive device using a controlled atomic layer removal process

The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer () over a spacer material () located over gate electrodes () and a doped region () located between the gate electrodes (), removing a portion of the spacer material () and the protective layer () located over the gate electrodes (). A remaining portion of the spacer material () remains over the top surface of the gate electrodes () and over the doped region (), and a portion of the protective layer () remains over the doped region (). The method further comprises removing the remaining portion of the spacer material () to form spacer sidewalls on the gate electrodes (), expose the top surface of the gate electrodes (), and leave a remnant of the spacer material () over the doped region (). Source/drains are formed adjacent the gate electrodesand through the remnant of the spacer material (), and a metal is incorporated into the gate electrodes ().

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Murphy, TX, United States of America

Steven Arthur Vitale