Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Steven Alfred Kummerl

Benjamin Stassen Cook

Sreenivasan Kalyani Koduri

Yuh-Harng Chien

Bernhard P Lange

Hung-Yu Chou

Juan Alejandro Herbsommer

Anthony Louis Coyle

Bo-Hsun Pan

Rajen Manicon Murugan

Abram M Castro

Kurt Peter Wachtler

Matthew David Romig

Wei-Yan Shih

Leslie Edward Stark

Bernhard Peter Lange

Jie Chen

Wai Lee

Jo Bito

Matthew John Sherbin

Saumya Gandhi

Ubol Udompanyavit

Gerald William Steele

Fu-Kang Lee

Kapil Heramb Sahasrabudhe

Jason Marc Cole

Fu-Hua Yu

Taylor R Efland

Peter Smeys

Barry Jon Male

Simon Joshua Jacobs

Christopher Daniel Manack

Robert Allan Neidorff

Yiqi Tang

Daniel Lee Revier

Michael G Amaro

Roberto Giampiero Massolini

Rongwei Zhang

Paul Merle Emerson

Chih-Chien Ho

Joyce Marie Mullenix

Makarand Ramkrishna Kulkarni

Liang Wan

Django Trombley

Frank Yu

Jeffrey Gail Holloway

James Huckabee

Richard J Saye

Pi-Chiang Huang

Dongbin Hou

Chi-Chen Chien

Stanley Chou

An integrated filter optical package including an ambient light sensor that incorporates an infrared (IR) filter in an integrated circuit (IC) stacked-die configuration is provided. The integrated filter optical package incorporates an infrared (IR) coated glass layer to filter out or block IR light while allowing visible (ambient) light to pass through to a light sensitive die having a light sensor. The ambient light sensor detects an amount of visible light that passes through the IR coated glass layer and adjusts a brightness or intensity of a display screen on an electronic device accordingly so that the display screen is readable.

Integrated filter optical package

A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

Semiconductor package with shunt and patterned metal trace

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

Floating die package

A method to improve transistor performance uses a wafer () of single-crystalline semiconductor with a first zone () of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth () farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone () of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Method for improving transistor performance

A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.

Custom leadframe from standard plus printed leadframe portion

An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.

Mechanical couplings designed to resolve process constraints

In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

Film covers for sensor packages

An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.

Integrated circuit chip with a vertical connector

In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.

Exposed heat-generating devices

In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

Packages with multiple exposed pads

A method for forming a semiconductor structure includes curing a shape memory polymer in a first shape. The shape memory polymer is coupled to a conductive layer. The method further includes folding the shape memory polymer from the first shape into a second shape. The method also includes bonding a semiconductor wafer to the conductive layer while the shape memory polymer is in the second shape. The semiconductor wafer has first and second dies. The semiconductor wafer is then singulated to separate the first die from the second die. The method further includes expanding the shape memory polymer to its first shape and singulating the shape memory polymer to separate the first and second dies.

Shape memory polymer for use in semiconductor device fabrication

Semiconductor devices and methods and apparatus to produce such semiconductor devices are disclosed. An integrated circuit package includes a lead frame including a die attach pad and a plurality of leads; a die including a MEMs region defined by a plurality of trenches, the die electrically connected to the plurality of leads; and a mold compound covering portions of the die, the mold compound defining a cavity between a surface of the die and a surface of the mold compound, wherein the mold compound defines a vent.

Semiconductor devices and methods and apparatus to produce such semiconductor devices

An integrated circuit (IC) package comprises a semiconductor die, a leadframe comprising a plurality of leads coupled to bond pads on the semiconductor die, and an electrically conductive member electrically coupled to the leadframe. A magnetic mold compound encapsulates the electrically conductive member to form an inductor. A non-magnetic mold compound encapsulates the semiconductor die, the leadframe, and the magnetic mold compound.

Integrated inductor with magnetic mold compound

An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.

Electronic device with three dimensional thermal pad

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Carrollton, TX, United States of America

Steven Alfred Kummerl