Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Steven Alan Lytle

Daniel Joseph Vitkavage

Mary Drummond Roby

Kurt George Steiner

Allen Yen

Robert Alan Ashton

Sailesh Chittipeddi

Simon John Molloy

Yaw S Obeng

Nace Layadi

Taeho Kook

Avinoam Kornblit

Susan Clay Vitkavage

Chong-Cheng Fu

Scott Jessen

Gerald W Gibson, Jr

Morgan J Thoma

Thomas Michael Wolf

Brian David Crevasse

Tungsheng Yang

Eric John Persson

Wan Yee Cheung

The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

Define via in dual damascene process

The present invention provides a method of forming integrated circuit interconnect structures wherein a passing metal feature does not include a landing pad. In an exemplary embodiment, the method includes forming a via opening through first and second dielectric layers, such as silicon dioxide layer, located over a conductive layer, such as copper, and to a first etch stop layer, such as silicon nitride, located over the conductive layer. A trench opening is then formed through the second dielectric layer and to a second etch stop layer. Once the via and trench openings are formed, an etch is conducted that etches through the first etch stop layer such that the opening contacts the underlying conductive layer.

Dual damascene process with no passing metal features

A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N&#x2014;H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N&#x2014;H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide. The hardmask and etch-stop layer enable the formation of a dual-damascene opening in the film stack, and the film structure of the present invention precludes N&#x2014;H base groups from diffusing from the low-k dielectric films and neutralizing acid catalysts in the photoresist used to define the dual damascene opening.

Split barrier layer including nitrogen-containing portion and oxygen-containing portion

The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.

Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof

A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.

Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies

The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.

Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer

A method for stripping photoresist material (,) from a semiconductor substrate (,) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (,). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.

Process for photoresist rework to avoid sodium incorporation

A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.

Transistor fabrication method

A process for forming a P.sub.2 O.sub.5 layer suitable for diffusion doping polysilicon gates is disclosed. The inventive process has a reduced thermal budget and helps to eliminate subsequent gate oxide roughness.

Growing community of inventors

Orlando, FL, United States of America

Steven Alan Lytle