Unisys Corporation

Steven A Thompson

Philip A Murphy

Robert H Tickner

Gary C Wu

Edward J Pullin

Wayne A Genetti

Chandra S Pawar

Gunnar K Gunnarsson

The present invention provides a multi-level memory system with a multi-level memory structure and methods for allocating data among the levels of memory based on the likelihood of imminent future use. The multi-level memory structure includes a first level memory that stores the data most likely to be imminently accessed, a second level memory that stores data transferred from the first level memory when the first level memory is full, and a third level memory that stores data that is the least recently used when the second level memory is full. According to the invention, predetermined criteria and statistics are used to determine which data is likely to be imminently accessed. Once the first level memory has been full, data stored in that memory level may be rearranged based on when it is likely to be accessed. The first level memory also provides for faster access than the second level memory which in turn provides faster access then the third level memory. The data in the second level memory is maintained according to a first-in-first-out algorithm. A task control processor controls the data allocation in the multi-level memory.

Multi-level memory and methods for allocating data most likely to be

A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.

Dedicated processor for task I/O and memory management

Growing community of inventors

Coatesville, PA, United States of America

Steven A Thompson