Intel Corporation

Steven A Peterson

Razi Uddin

Chee How Lim

Usman Mughal

Haran Thanigasalam

Geoffrey A Gould

Chunyu Zhang

Vishal Sharma

Kiriti Bhagavathula

Lee Hayashida

Sriram Sri Balasubrahmanyam

Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.

Device, apparatus and system to reduce current leakage during differential communications

An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.

Jitter tolerant receiver

In accordance with a universal nonvolatile memory boot mode, one or more portions of boot code are obtained from a nonvolatile memory component. These one or more portions are obtained without knowing a row size used by the nonvolatile memory component, a column address strobe (CAS) latency used by the nonvolatile memory component, or a default burst length used by the nonvolatile memory component. The one or more portions of boot code are executed to configure the system to access a volatile memory component, and/or to reconfigure the system to access the nonvolatile memory in a different mode of operation.

Universal nonvolatile memory boot mode

A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.

Method and apparatus for generating multiple system memory drive strengths

A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

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Placerville, CA, United States of America

Steven A Peterson