International Business Machines Corporation

Steven A King

Timothy B Brodnax

Dale A Rickard

Bryan Keith Bullis

Daniel L Stanley

Peter Michael Kogge

James D Allen

John Stanley Bialas, Jr

Johnny James LeBlanc

Robert L Schoenike

Clark J Spencer

A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Synchronizing a prediction RAM

A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Shadow register file for instruction rollback

A computer memory system having partitioned page address for instructions and operands. The partitioning scheme for the virtual addressing memory minimizes the delay between the translation logic and the page translation RAMs. Computer processor performance is delayed by only a single clock cycle by the sharing of the memory address bus control between two address processors.

Partitioning of virtual addressing memory

A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

Data processing system having prediction by using an embedded guess bit

A system and method for managing the nonvolatile memory capacity of individual workstations within a data processing network having a multiplicity of workstations with resident nonvolatile memory devices. In the context of the embodying network, the invention provides for a selective querying of workstations to determine unused disk capacity, a comparison of such capacity to a threshold defined for the respective workstation, and the generation of an event message indicating sub-threshold capacity. The event is subject to local or network logging, and can include information identifying the workstation and its disk capacity status. A refinement of the invention contemplates the reallocation of disk capacity within the network to avoid premature termination of programs executing on a workstation upon the finding of a sub-threshold capacity in the workstation.

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Herndon, VA, United States of America

Steven A King