Skyworks Solutions, Inc.

Steve Xin Liang

Anthony James Lobianco

Robert W Warren

Qing Gan

A flip chip packaged component includes a die having a first surface and a dielectric barrier disposed on the first surface of the die. The dielectric barrier at least partially surrounds a designated location on the first surface of the die. A plurality of bumps is disposed on the first surface of the die on an opposite side of the dielectric barrier from the designated location. The flip chip packaged component further includes a substrate having a plurality of bonding pads on a second surface thereof. A cavity is defined by the first surface of the die, the dielectric barrier, and the substrate. A molding compound encapsulates the die and at least a portion of the substrate.

Integrated circuit package including in-situ formed cavity

A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.

In-situ cavity integrated circuit package

A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the copper portion. The process includes positioning the die on the substrate such that the bonding cap of each copper pillar bump of the plurality of copper pillar bumps contacts a corresponding respective one of a plurality of bonding pads on the substrate, and thermosonically bonding the die to the substrate.

Thermal mechanical flip chip die bonding

According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

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San Diego, CA, United States of America

Steve Xin Liang