International Business Machines Corporation

Steve Woolet

Gordon Taylor Davis

Jeffrey Haskell Derby

Srinivasan Ramani

Ken Van Vu

Anil Krishna

Gordon Bernard Bell

A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

Prefetching with multiple processors and threads via a coherency bus

Effective prefetching with multiple processors and threads

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Raleigh, NC, United States of America

Steve Woolet