Integrated Silicon Solution Incorporated

Silicon Access Networks, Inc.

Steve W Lim

Subramani Kengeri

Yong H Jiang

A content addressable memory (CAM) with built-in power saving management. The CAM includes a comparator circuit region that is coupled to a match line (ML) as well as a swing line (SL). The comparator circuit region is coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a pre-charge voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing) while the SL charge shares with the Ml. Advantageously, in response to this data mismatch, the SL charge shares with the ML such that Vswing is approximately less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground. Thus, because Vswing is as large as Vc in a conventional CAM whereas Vswing is as large as about Vc/2 in the invention, the invention's Vswing restriction provides significant more power saving.

Charge shared match line differential generation for CAM

A Random Access Memory (RAM) with improved memory access time supporting simultaneous transitions of an address signal and a write enable signal while preventing accidental writes. The RAM includes a memory array, an address transition detector and a race detector. Operation of the memory array is controlled by the address signal and a write clock signal. In response to the write clock's read state the memory array reads data from an address represented by the address signal, while the write clock's write state causes the memory array to write data at the address represented by the address signal. The address transition detector and race detector work together to generate the write clock signal. The address transition detector generates an address transition signal when it detects a transition of the address signal from a representation of a first address of the memory array to a representation of a second address of the memory array. The address transition signal is coupled to the race detector, which, if the write clock is currently in its write state, forces the write clock to its read state before the address signal propagates to the memory array.

Apparatus and method for preventing accidental writes from occurring due

The present invention is dynamic pulse generator for generating an output pulse from a first input pulse and a second input pulse, where the output pulse is guaranteed to have a pulse width of at least the pulse width of whichever of the two input pulses has a delayed leading edge with respect to the other. The first input pulse has a first leading edge and a first trailing edge. The second input pulse has a second leading edge and a second trailing edge. The second leading edge is delayed from the first leading edge. An edge detector detects the second leading edge, and outputs a first predetermined level when the second leading edge is detected. The edge detector also detects the first trailing edge and the second trailing edge and outputs a second predetermined level. A latch is responsive to the edge detector and generates a signal indicating that the second leading edge has been detected. The latch maintains the output of the edge detector at the first predetermined level until the edge detector detects both the first trailing edge and the second trailing edge.

Guaranteed dynamic pulse generator

A wordline wakeup circuit for use in a static memory responsive to an external clock signal and chip enable signals provided by a controller/microprocessor to perform a memory operation on the static memory. The wordline wakeup circuit receives a global clock (GCLK) signal generated by memory control circuitry from the external clock signal and a word line enable (WLEN) signal asserted by the control circuitry when the chip enables indicate a pending memory operation. The wordline wakeup circuit asserts a wordline wakeup signal (LWLEN) signal as soon as possible after the GCLK signal goes high. The LWLEN signal when asserted activates decoder circuity to assert wordlines as necessary to perform the memory operation. If the WLEN signal is provided, the wordline wakeup circuit keeps the LWLEN signal high for at least the high portion of the GCLK signal, enabling the decoder to execute the memory operation, if the WLEN signal is not provided, the wordline wakeup circuit drops the LWLEN signal. The short pulse made by the LWLEN signal when there is no pending memory operation does not affect the decoder.

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Cupertino, CA, United States of America

Steve W Lim