Micron Technology Incorporated

Micron Semiconductor, Inc.

Steve W Heppler

Chad A Cobbley

Michael B Ball

Rich Fogal

An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.

Electrical interconnect using locally conductive adhesive

An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.

There is an IC (integrated circuit) testing devicethat receives singulated ICs from a singulation station's bottom table, where an IChas slid down onto loading ramp or track. The IC will slide into test station, where stop pinhas been inserted to stop the IC in DUT (device under test) station. In the DUT station, the IC is securely held in position by an extractor bar, insertion bar, and a part guide. Thereby, test cite stationwill move downward and insert ICinto testing socket. After testing the IC, testing stationreturns upward with IC in the same secured position. Pinwill be removed to allow the IC to slide into part holding station. If the IC was not defective, pinwill be removed to allow the IC to slide onto trackof the IC separator station. While the test cite stationis in the up position a second IC is slid along trackand loaded into DUT citebeing readied for the next test cycle. However, if the first IC was found to be defective, pinwill be positioned so as to stop the IC from sliding onto track. Thereby, the test citewill proceed to the down position to test the second IC, and simultaneously pinwill be removed to now allow the defective IC to slide onto track. The second IC has now completed its testing and is ready to proceed to the remainder of the cycle.

Method and apparatus for testing integrated circuits

A method and apparatus are provided for handling planar structures, such as semiconductor wafers, with reduced breakage and cracking. The method includes the step of segmenting a wafer prior to grinding. The apparatus includes a segmented vacuum table for supporting wafer portions in position to be ground to a desired thickness. In another aspect of the invention, adhesive material is employed to individually secure wafer portions in position during the grinding process.

Method and apparatus for processing a planar structure

Apparatus for processing a planar structure

A method and system for fabricating electronic assemblies, such as multi chip modules, which include wire bonded semiconductor dice, are provided. Initially, dice having bond pads, and a substrate having corresponding bond pads, are provided. Using a wire bonding process, bonded connections are made between the bond pads on the dice, and the bond pads on the substrate. During the wire bonding process, electrical continuity in the bonded connections can be evaluated. Following wire bonding, but prior to subsequent processing of the assemblies, quick functionality tests can be performed to evaluate other electrical characteristics of the assemblies (e.g., gross functionality, open/short, pad leakage, cell defects). This permits defective assemblies to be identified prior to further processing. Once the assemblies have been completed, full functionality and parametric tests can be performed. An assembly for performing the method includes a conventional wire bonder; a tester having test circuitry for performing the required tests; and an electrical connector for establishing temporary electrical communication with the assembly.

System for fabricating and testing assemblies containing wire bonded

Method and system for fabricating and testing assemblies containing wire

There is an IC (integrated circuit) testing device 11 that receives singulated ICs from a singulation station's bottom table 44, where an IC 15 has slid down onto loading ramp or track 16. The IC will slide into test station 18, where stop pin 22 has been inserted to stop the IC in DUT (device under test) station 20. In the DUT station, the IC is securely held in position by an extractor bar 26, insertion bar 28, and a part guide 24. Thereby, test cite station 18 will move downward and insert IC 15 into testing socket 30. After testing the IC, testing station 18 returns upward with the IC in the same secured position. Pin 22 will be removed to allow the IC to slide into part holding station 31. If the IC was not defective, pin 32 will be removed to allow the IC to slide onto track 36 of the IC separator station 34. While the test cite station 18 is in the up position a second IC is slid along track 16 and loaded into DUT cite 20 being readied for the next test cycle. However, if the first IC was found to be defective, pin 32 will be positioned so as to stop the IC from sliding onto track 36. Thereby, the test cite 18 will proceed to the down position to test the second IC, and simultaneously pin 32 will be removed to now allow the defective IC to slide onto track 38. The second IC has now completed its testing and is ready to proceed to the remainder of the cycle.

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Boise, ID, United States of America

Steve W Heppler