Micron Technology Incorporated

Aptina Imaging Corporation

Steve V Cole

Scott James Derner

Toby D Robbs

Howard E Rhodes

Fatma Arzum Simsek-Ege

Charles L Ingalls

Michael Amiel Shore

J Wayne Thompson

Benjamin A Millemon

Tyler A Lowrey

Kunal R Parekh

Monte Manning

Suraj J Mathew

An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

Memory arrays with vertical transistors and the formation thereof

Some embodiments include an apparatus having memory cells which include capacitors. Bitline pairs couple with each of the memory cells. One of the bitlines within each bitline pair corresponds to a first comparative bitline and the other of the bitlines within each bitline pair corresponds to a second comparative bitline. The bitline pairs extend to sense amplifiers which compare electrical properties of the first and second comparative bitlines to one another. The memory cells are subdivided amongst a first memory cell set using a first set of bitline pairs and a first set of sense amplifiers, and a second memory cell set using a second set of bitline pairs and a second set of sense amplifiers. The second set of bitline pairs has the same bitlines as the first set of bitline pairs, but in a different pairing arrangement as compared to the first set of bitline pairs.

Apparatuses comprising memory cells, and apparatuses comprising memory arrays

A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

DRAM sense amplifier active matching fill features for gap equivalence systems and methods

A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of the image sensor. In one embodiment, dark current is reduced by providing a deep n-type region having an n-type peripheral sidewall formed in a p-type substrate region underlying a pixel array region to separate the pixel array region from a peripheral circuitry region of the image sensor. The method and structure also provide improved protection from blooming.

Image sensor for reduced dark current

The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.

Methods of forming memory circuitry

A process for forming low resistance contacts between silicide areas and upper level polysilicon interconnect layers including a specific doping technique that provides solid low resistance contacts between a lower level of a silicided area and an upper level polysilicon interconnect. The doping technique combines a doping implant of the upper level polysilicon and an ion-mixing implant into a single implant thereby achieving a low resistive implant which also reduces processing steps.

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Boise, ID, United States of America

Steve V Cole