Imec Vzw

Imec

Pulsify Medical

Steve Stoffels

Stefaan Decoutere

Brice De Jaeger

Marleen Van Hove

Niels Posthuma

Hu Liang

Yoganand Saripalli

Daniel Barbosa

Jan D'HOOGE

Rodrigo Bastos Moraes

A method for manufacturing an III-nitride semiconductor structure is provided. The method includes providing a substrate comprising a first layer having an upper surface of monocrystalline III-nitride material; providing, over the upper surface, a patterned dielectric layer comprising a first dielectric feature; loading the substrate into a process chamber; exposing the substrate to a first gas mixture comprising at least one Group III-metal organic precursor gas, a nitrogen containing gas and hydrogen gas at a predetermined temperature, thereby forming, on the upper surface, a second layer of a monocrystalline III-nitride material by area selective growth wherein two opposing sidewalls of the dielectric feature are oriented parallel to one of the {11-20} crystal planes of the first layer such that upon formation of the second layer of the monocrystalline III-nitride material, a first trench having tapered sidewalls is formed so that the crystal plane of the second layer parallel to the tapered sidewalls is one of the {1-101} crystal planes.

Method for manufacturing a vertical power device including an III-nitride semiconductor structure

A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

Group III-nitride based vertical power device and system

Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

Enhancement-mode high electron mobility transistor

A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat.

3D power device and system

An enhancement-mode transistor and method for forming a gate of an enhancement-mode transistor are provided. The method includes: (a) providing a p-doped AlGaInN gate layer, consisting of a first part and a second part on top of the first part, above a p-doped AlGaInN channel layer of an enhancement-mode transistor under construction; and (b) providing a metal gate layer on the top surface of the second part, the metal gate layer being formed of a material such as to form a Schottky barrier with the second part, wherein providing the p-doped AlGaInN gate layer comprises the steps of: (a1) growing the first part above the p-doped AlGaInN channel layer of the enhancement-mode transistor under construction, the first part having an average Mg concentration of at most 3&#xd7;10atoms/cm, and (a2) growing the second part on the first part, the second part having an average Mg concentration higher than 3&#xd7;10atoms/cmand having a top surface having a Mg concentration higher than 6&#xd7;10atoms/cm.

Gate for an enhancement-mode transistor

The present disclosure is related to a III-Nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (MCL) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. The present disclosure is also related to a method for producing a device according to the present disclosure.

III-nitride based semiconductor device with low vulnerability to dispersion and backgating effects

The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

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Haasrode, Belgium

Steve Stoffels