Intel Corporation

Steve Spangler

Subramaniam M Maiyuran

Niranjan L Cooray

Vladimir M Pentkovski

Salvador Palanca

Angad Narang

Steve Tsai

Jagannath Keshava

Hsien-Hsin Lee

Praveen B Mosur

Suresh N Kuttuva

A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.

Method and apparatus for prefetching data into cache

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El Dorado Hills, CA, United States of America

Steve Spangler