Microsoft Technology Licensing, LLC

Steve Pronovost

Anuj Bharat Gosalia

Ameet Arun Chitre

Rudolph Balaz

Maxwell Simon Abernethy

Leonardo Esteban Blanco

Reiner Fink

Michael Paul Erich Von Hippel

Zhigang Xu

Bryan L Langley

Zachary Scott Northrup

Ana Marta Amaral De Carvalho

Hrushit Kamal Parikh

Amar Dinesh Patel

Blake Douglas Pelton

Donald Scott MacDonald

Glenn Frederick Evans

Patrik Schnell

David R Blythe

David Hepkin

Max Alan McMullen

Jason Stewart Wohlgemuth

Oreste Dorin Ungureanu

Aditya Bhandari

Jin Lin

Michael Bishop Ebersol

Sandeep Prabhakar

Lucia Darsa

Andrew Zicheng Yeung

Harneet Singh Sidhana

Mohamed Sadek

Bennett Sorbo

Kapil Vaswani

Attilio Mainetti

Jesse Natalie

Antoine Jean Denis Delignat-lavaud

Steven Adrian West

Hideyuki Nagase

Alexander Daniel Grest

Emily Cara Clemens

Dexuan Cui

Michael Halstead Kelley

Sarah Elizabeth Stephenson

Carolina Cecilia Perez-vargas

Anuj B Gossalia

Benjamin M Cumings

Max Mcmullen

Methods, systems, and computer program products for direct assignment of physical devices to confidential virtual machines (VMs). At a first guest privilege context of a guest partition, a direct assignment of a physical device associated with a host computer system to the guest partition is identified. The guest partition includes the first guest privilege context and a second guest privilege context, which is restricted from accessing memory associated with the first guest privilege context. The guest partition corresponds to a confidential VM, such that a memory region associated with the guest partition is inaccessible to a host operating system. It is determined, based on a policy, that the physical device is allowed to be directly assigned to the guest partition. Communication between the physical device and the second guest privilege context is permitted, such as by exposing the physical device on a virtual bus and/or forwarding an interrupt.

Direct assignment of physical devices to confidential virtual machines

Dynamic refresh rate (DRR) switching is used to dynamically update a refresh rate of content presented on an interface. When a first application and a second application are presented on a user interface at a first refresh rate; a request may be received to temporarily boost the first refresh rate to a second, higher, refresh rate. DRR switching is initiated as the first refresh rate is temporarily boosted to a second refresh rate. Applications that are opted in to the second refresh rate receive signals to refresh content at the second refresh rate, while applications that are not opted in to the second refresh rate receive signals to refresh content at a virtualized refresh rate that matches the first refresh rate. Thus, the first application refreshes content at the first refresh rate and the second application refreshes content at the second, higher refresh rate, providing a smooth user experience without unnecessarily utilizing power consumption.

Dynamic refresh rate switching system and method thereof

Dynamic refresh rate switching

The described technology addresses one or more of the foregoing problems by receiving one or more workloads from an application. Each of the one or more graphics workloads are associated with completion deadline information and execution metadata representing execution guidance for the workload. The described technology further generates a processor performance adjustment for each of the one or more workloads using a performance model providing the processor performance adjustment based on the completion deadline information and the execution metadata for each of the one or more workloads. The described technology further communicates each of the one or more received workloads and its corresponding generated processor performance adjustment to a processor subsystem. Each of the processor performance adjustments instructs the processor subsystem on a processor adjustment to be implemented when executing the associated workload.

Dynamic processor power management

Examples described herein generally relate to rendering graphics using a graphics processing unit (GPU) in a computing device. A synchronization object associated with a wait event can be created, wherein the wait event indicates a time offset before a timed event associated with a display device of the computing device. A plurality of rendering instructions for the GPU can be stored in a buffer, wherein the plurality of rendering instructions can be received from an application before a release of the synchronization object. Release of the synchronization object can be detected based on occurrence of the wait event, and the plurality of rendering instructions can be sent from the buffer to at least a portion of the GPU based on detecting the release of the synchronization object.

Techniques for reducing perceptible delay in rendering graphics

Methods and devices for presenting a virtual reality image may include rendering at least one image frame received from an application for a virtual reality image for display on a display device. The methods and devices may include receiving a selection of one of a plurality of tear thresholds that define conditions for tearing in a displayed image. The methods and devices may include determining whether the rendered frame is received prior to the selected one of the plurality of tear thresholds, wherein the selected one of the plurality of tear thresholds occurs after a frame timing event that corresponds to a deadline for initiating display of a new frame. The methods and device may include communicating the rendered image frame to the display device for presentation on the display device when the rendered frame is received prior to the selected one of the plurality of tear thresholds.

Low latency tearing without user perception

Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

Memory management techniques

A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.

System and method for layering using tile-based renderers

Techniques for minimizing coprocessor 'starvation,' and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called 'surface faulting' allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a &#x201c;fence,&#x201d; a &#x201c;trap&#x201d; and a &#x201c;enable/disable context switching,&#x201d; can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a &#x201c;flip&#x201d; technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.

Building a run list for a coprocessor based on rules when the coprocessor switches from one context to another context

Embodiments described herein relate to improving throughput of a CPU and a GPU working in conjunction to render graphics. Time frames for executing CPU and GPU work units are synchronized with a refresh rate of a display. Pending CPU work is performed when a time frame starts (a vsync occurs). When a prior GPU work unit is still executing on the GPU, then a parallel mode is entered. In the parallel mode, some GPU work and some CPU work is performed concurrently. When the parallel mode is exited, for example when there is no CPU work to perform, the parallel mode may be exited.

CPU-GPU parallelization

Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A 'run list' may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.

Multithreaded kernel for graphics processing unit

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Redmond, WA, United States of America

Steve Pronovost