Artisan Components, Inc.

Steve P Kornachuk

Scott T Becker

Craig R Silver

A low power bank architecture implemented in memory access circuitry is disclosed. The bank architecture includes a bank circuit that has a bank core integrated with a pair of bitlines and a bank interface circuit that is coupled to the pair of bitlines. The bank architecture further includes a global data bus pair that is configured to communicate a less than full rail voltage swing. The global data bus pair is coupled to the bank interface circuit of the bank circuit that is designed to convert the less than full rail voltage swing into an up to about full rail voltage swing that is communicated to the pair of bitlines. The bank circuit is configured to be replicated once for each of the pair of bitlines in a memory core having an array of bank cores. By communicating memory access signals, such as differential write data, at a less than full rail voltage over the global data bus pair, a substantial amount of power is saved, which provides excellent power savings for many electronic device applications.

Low power differential signal transition techniques for use in memory

A programmable memory test interface for testing a memory device is disclosed. The interface includes a plurality of programmable input pins and output pins. The interface also includes a logic interfacing means for connecting external signals to the plurality of programmable input pins and output pins. The external signals are processed by the logic interfacing means and then communicated to a plurality of memory connection pins that couple up to the memory device. The logic component means is capable of being configured in accordance with one or more memory testing methodologies including a serial built-in-self-test (BIST), a parallel built-in-self-test (BIST), a parallel test, a serial test, and a scan test. The configuring is performed by selectively interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface means in a test mode that operates in one or more memory testing methodologies or a mission mode.

Programmable universal test interface for testing memories with

A memory circuit that includes a memory core having an array of core cells is provided. The array of core cells are coupled to a plurality of wordlines and a plurality of bitline pairs. The memory circuit further includes a self-timing path that has a model core cell that is coupled to a model wordline, and the model wordline is driven by a model wordline driver. The self-timing path also includes a model sense amplifier that is coupled to the model core cell through a pair of model bitlines. The model wordline and the pair of model bitlines are each coupled to a plurality of dummy core cells to approximate an RC delay of a worst case core cell of the array of core cells. Further, the model wordline is a folded wordline, such that the model wordline has a termination at a location that is proximate to the model wordline driver.

High speed memory self-timing circuitry and methods for implementing the

Disclosed is a programmable memory test interface. The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuitry. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuitry, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.

Programmable universal test interface and method for making the same

Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferably includes a balanced circuit having a set of first transistors and a set of second transistors. The set of first transistors being wired diagonally across the set of four substantially self enclosing gate transistors. In a preferred embodiment, the set of second transistors are wired diagonally across the set of four substantially self enclosing gate transistors in a manner that ensures that the set of second transistors are wired substantially perpendicular to the set of first transistors.

Integrated circuit layout methods and layout structures

Disclosed is a method for amplifying a data signal read from a memory device. The method includes sensing an initial voltage difference across a data bus that is coupled to the memory device. Producing an initial voltage difference across a sensed data bus after the sensing detects the initial voltage difference. The initial voltage difference is configured to partially separate a pair of nodes associated with the sensed data bus. The method further includes subsequently isolating the data bus from the sensed data bus to rapidly further separate the pair of nodes associated with the sensed data bus, the rapid separation producing the amplified data signal across the sensed data bus.

Voltage sense amplifier and methods for implementing the same

Disclosed is an apparatus for generating a memory access signal. The apparatus includes a latch having a set state for driving a set transistor, and a reset state for driving a reset transistor. The latch having an input terminal and an output terminal, and the latch transitions between the set and reset states in accordance with a system clock signal. The apparatus further includes a driver coupled to the output terminal of the latch for producing an access signal, and feedback path for feeding back the access signal to the input terminal of the latch. Wherein the latch operates to switch from the set state to the reset state in accordance with the fed back access signal. In this manner, the system clock is isolated from the set transistor when the latch is already in the set state. Further, the latch operates to switch from the reset state to the set state in accordance with the fed back access signal, such that the system clock is isolated from the reset transistor when the latch is already in the reset state.

High speed addressing buffer and methods for implementing same

Disclosed is a latch sense amplifier output buffer for amplifying a data signal read from a memory. The latch sense amplifier output buffer includes a sense amplifier core having an amplifier circuit. The amplifier circuit provides amplification on the data signal read from a random access memory cell location. The sense amplifier core is preferably configured to generate an amplified data signal. Further included is an output data latching circuit that is configured to substantially simultaneously store the amplified data signal and generate an output data signal. An output buffer core includes an output driver circuit having a pull up transistor and a pull down transistor. The output driver circuit substantially concurrently receives the amplified data signal from the sense amplifier core and the output data signal from the output data latching circuit. The amplified data signal provides a fast turnoff to the pull up or pull down transistor, to thereby generate a rapid output at an output node coupled to the other pull up or pull down transistor.

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San Jose, CA, United States of America

Steve P Kornachuk